FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing

Lee, Chun-Yi; Jha, Niraj K.

doi:10.1109/iccd.2009.5413133

Cited by 14 publications

(8 citation statements)

References 23 publications

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“…In order to enable the ABGB technique for VPSRDPM, we incorporate voltage generators into the buffer banks and the crossbar to supply the required voltages to the back gates of FinFETs. Details of the voltage generator design are provided in [20]. The size of the voltage generator is 1.225 μm×2.745 μm.…”

Section: Vpsrdpmmentioning

confidence: 99%

“…Hence, it provides a complete simulation framework to simulate the power consumption based on the traffic in the network. We have developed GARNET-FinFET [20], which is based on the original GAR-NET. GARNET-FinFET incorporates ORION-FinFET [22], which is able to simulate the power/performance of a FinFETbased interconnection network.…”

Section: A Simulation Setupmentioning

confidence: 99%

“…We employ a power/performance simulation platform which we previously developed specifically for FinFET-based interconnection networks to make VPSR simulation possible. A preliminary version of this paper was presented in [20].…”

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confidence: 99%

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Variable-Pipeline-Stage Router

Lee

Jha

2013

IEEE Trans. VLSI Syst.

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On-chip interconnection networks are fast becoming significant power consumers in high-performance chip multiprocessors. Increased power consumption leads to more heat, degrades system reliability, and may increase the cost of cooling integrated circuit packages. This situation is becoming worse as bulk CMOS technology scales further into the nanometer regime because of the excessive leakage power caused by shortchannel effects. In this paper, we explore the use of Fin-FETs, which are promising substitutes for bulk CMOS at the 22-nm node and beyond, to design on-chip network routers. We present a detailed design of a variable-pipeline-stage router (VPSR) targeted at FinFET technology. We employ a dynamic power management scheme, which we call adaptive back-gate biasing, for FinFET implementations. We propose enhanced token flow control (ETFC), a flow control mechanism that improves upon the energy/delay/throughput of the previous stateof-the-art token flow control mechanism. We evaluate VPSR and ETFC on a simulation platform specifically designed for power/performance simulations of FinFET-based interconnection networks. The results show that VPSR is able to successfully adapt its power consumption to incoming traffic, with a resultant 21.5% reduction in power with almost no impact on latency.

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Section: Vpsrdpmmentioning

confidence: 99%

Section: A Simulation Setupmentioning

confidence: 99%

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Variable-Pipeline-Stage Router

Lee

Jha

2013

IEEE Trans. VLSI Syst.

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“…It is also possible to independently control the two transistor gates of FinFETs. This enables design of creative circuit modules [4], and dynamic power and thermal management schemes [5]. FinFETs also enable higher transistor density, because fin height determines effective channel width.…”

Section: Introductionmentioning

confidence: 99%

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

Tang

Yang

Lee

et al. 2015

IEEE Trans. VLSI Syst.

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As technology has moved into the deepsubmicrometer regime, the shrinking feature size has placed a considerable stress on CMOS fabrication due to short-channel effects (SCEs) and excessive leakage. Although many research efforts have been devoted to seeking system-level solutions, underlying transistor-level solutions are still urgently required to overcome these obstacles. FinFETs have emerged as promising substitutes for conventional CMOS due to their superior control of SCEs and process scalability. However, FinFETs still face lithographic and workfunction engineering challenges, in addition to those posed by supply voltage and temperature variations across the integrated circuit (IC). These lead to process, supply voltage, and temperature (PVT) variations in FinFET ICs, which, in turn, lead to large spreads in delay and leakage. In this paper, we present a multicore power, area, and timing (McPAT)-PVT, an integrated framework for the simulation of power, delay, as well as PVT variations of FinFET-based processors. McPAT-PVT uses a FinFET design library, consisting of logic and memory cells, to model circuit-level characteristics as well as their PVT variation trends. It is based on macromodels, derived from very accurate TCAD device simulations that characterize various functional units in a processor under PVT variations, making yield analysis for timing and power for processor components possible. McPAT-PVT can model both shorted-gate (SG) and asymmetric-workfunction shorted-gate (ASG) FinFET-based processors. Combining these macromodels with a FinFET-based CACTI-PVT cache model and an ORION-PVT on-chip network model, McPAT-PVT is able to simulate a delay and power consumption of all processor components under PVT variations.We present extensive simulation results to demonstrate its efficacy, including for an alpha-like processor and multicore simulations based on Princeton Application Repository for Shared-Memory Computers benchmarks. Results show that the ASG FinFET-based processor implementation has 73× lower leakage power and 2.6× lower total power relative to the SG FinFET-based processor implementation for the same performance, with <1% area penalty.

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“…Static knowledge of the traffic patterns obtained by compiler analysis was also used to optimize the frequency/voltage scaling of the individual interconnection links in the network [11]. Recent research proposes the adaptive use of back-gate biasing for managing the dynamic power of on-chip interconnect [9] and the dynamic redistribution of the power between the on-chip cores and routers to adapt to the variation in the computation and communication demands of applications [12].…”

Section: Related Workmentioning

confidence: 99%

Power-aware Manhattan Routing on Chip Multiprocessors

Benoît

Melhem

Renaud-Goud

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium

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Abstract:We investigate the routing of communications in chip multiprocessors (CMPs). The goal is to find a valid routing in the sense that the amount of data routed between two neighboring cores does not exceed the maximum link bandwidth while the power dissipated by communications is minimized. Our position is at the system level: we assume that several applications, described as task graphs, are executed on a CMP, and each task is already mapped to a core. Therefore, we consider a set of communications that have to be routed between the cores of the CMP. We consider a classical model, where the power consumed by a communication link is the sum of a static part and a dynamic part, with the dynamic part depending on the frequency of the link. This frequency is scalable and it is proportional to the throughput of the link. The most natural and widely used algorithm to handle all these communications is XY routing: for each communication, data is first forwarded horizontally, and then vertically, from source to destination. However, if it is allowed to use all Manhattan paths between the source and the destination, the consumed power can be reduced dramatically. Moreover, some solutions may be found while none existed with the XY routing. In this paper, we compare XY routing and Manhattan routing, both from a theoretical and from a practical point of view. We consider two variants of Manhattan routing: in single-path routing, only one path can be used for each communication, while multi-paths routing allows to split a communication between different routes. We establish the NP-completeness of the problem of finding a Manhattan routing that minimizes the dissipated power, we exhibit the minimum upper bound of the ratio power consumed by an XY routing over power consumed by a Manhattan routing, and finally we perform simulations to assess the performance of Manhattan routing heuristics that we designed.Key-words: routing; chip multiprocessor; energy; power; Manhattan; singlepath; multi-paths; complexity. inria-00629804, version 2 -6 Oct 2011Routage de Manhattan minimisant la puissance dissipée sur des processeurs multi-coeurs

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FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing

Cited by 14 publications

References 23 publications

Variable-Pipeline-Stage Router

Variable-Pipeline-Stage Router

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

Power-aware Manhattan Routing on Chip Multiprocessors

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