FinFET SRAM design challenges

Burnett, D.; Parihar, Sanjay; Ramamurthy, Hema; Balasubramanian, Sriram

doi:10.1109/icicdt.2014.6838606

Cited by 29 publications

(17 citation statements)

References 8 publications

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“…The never-ending demand for packing more functionality per area and the requirement of higher performance from processing units leads to continuous scaling of devices. 46 This scaling trickles down to smaller bitcells and enables an increase in memory array density in terms of number of bits stored per area. Hence from the density point of view, minimum sized transistors are desired in bitcells.…”

Section: Sram Designmentioning

confidence: 99%

“…The 1:1:1 bitcell provides highest array density but it suffers from flaws in terms of lower read stability and writability. 46,47 The constant need for voltage scaling to lower power further exacerbates SRAM readability and writability issues. This calls for alternate bitcells like the Low Voltage (LV) 1:1:2 cell and High Performance (HP) 1:2:2 cell 46 along with read and write assist techniques to improve SRAM metrics.…”

Section: Sram Designmentioning

confidence: 99%

“…46,47 The constant need for voltage scaling to lower power further exacerbates SRAM readability and writability issues. This calls for alternate bitcells like the Low Voltage (LV) 1:1:2 cell and High Performance (HP) 1:2:2 cell 46 along with read and write assist techniques to improve SRAM metrics. Several assist techniques 48,49 have been proposed and studied to improve SRAM performance and lower operational V min.…”

Section: Sram Designmentioning

confidence: 99%

See 2 more Smart Citations

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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It has been almost a decade since FinFET devices were introduced to full production; they allowed scaling below 20 nm, thus helping to extend Moore's law by a precious decade with another decade likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique structure, these 3-D transistors offer significant performance improvements and power reduction compared to planar CMOS devices. As we are entering into the sub-10 nm era, FinFETs have become dominant in most of the high-end products; as the transition from planar to FinFET technologies is still ongoing, it is important for digital circuit designers to understand the challenges and opportunities brought in by the new technology characteristics. In this paper, we study these aspects from the device to the circuit level, and we make detailed comparisons across multiple technology nodes ranging from conventional bulk to advanced planar technology nodes such as Fully Depleted Silicon-on-Insulator (FDSOI), to FinFETs. In the simulations we used both state-of-art industry-standard models for current nodes, and also predictive models for future nodes. Our study shows that besides the performance and power benefits, FinFET devices show significant reduction of short-channel effects and extremely low leakage, and many of the electrical characteristics are close to ideal as in old long-channel technology nodes; FinFETs seem to have put scaling back on track! However, the combination of the new device structures, double/multi-patterning, many more complex rules, and unique thermal/reliability behaviors are creating new technical challenges. Moving forward, FinFETs still offer a bright future and are an indispensable technology for a wide range of applications from high-end performance-critical computing to energy-constraint mobile applications and smart Internet-of-Things (IoT) devices.

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Section: Sram Designmentioning

confidence: 99%

Section: Sram Designmentioning

confidence: 99%

Section: Sram Designmentioning

confidence: 99%

See 1 more Smart Citation

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

View full text Add to dashboard Cite

show abstract

“…Similar review was also carried out by Bhattacharya and Jha [16]. Discussion on design challenges on FinFET was carried out by Burnett et al [17]. The most recent study of Zhang et al [18] [19] have emphasized on low powered applications with FinFET technologies of 7/8 nm.…”

Section: Existing Techniquesmentioning

confidence: 88%

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Girish¹,

Shashikumar²

2016

CAE

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With the advancement in the energy efficient storage system, FinFET has already gained a pace in the area of computational memory management. However, after reviewing the research work focusing on FinFET based SRAM cells till date, we found that amount of research work towards enhancement of the design principle has not been much in number. Hence, we study some of the recently introduced research contribution towards enhancing the design performance of FinFET based SRAM cells and found that majority of the technique have both advantages and limitations too. We also highlights the significant research gap from the existing studies in order to assist the readers aware of the practicality of the research progress in this regards.

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“…Therefore, each model has its configuration with a different distribution of fins in the cell's transistors. The SRAM cell structure is divided into three parts with their proper notation (PU:PG:PD), meaning respectively: Pull Up, Pass Gate and Pull Down [15]. As an example, the HD configuration adopts a (1:1:1) configuration, meaning that all the cell transistors are composed of a single fin.…”

Section: A Sram Cell Modeling In Tcadmentioning

confidence: 99%

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Copetti

Medeiros

Taouil

et al. 2020

2020 IEEE Latin-American Test Symposium (LATS)

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Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization allowed by FinFETs tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them and test escapes can occur. These undetected faults associated with weak resistive defects may affect the FinFET-based SRAM reliability during the lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed in order to allow the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFETbased SRAM cell. Results show that weak defects may have either a positive or negative influence on the cell reliability against SEUs caused by ionizing particles.

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FinFET SRAM design challenges

Cited by 29 publications

References 8 publications

Back to the Future: Digital Circuit Design in the FinFET Era

Back to the Future: Digital Circuit Design in the FinFET Era

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

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