FinFET technology for future microprocessors

Ludwig,; Aller,; Gernhoefer,; Keinert,; Nowak, Bernadeta; Joshi,; Müeller,; Tomaschko,

doi:10.1109/soi.2003.1242886

Cited by 19 publications

(10 citation statements)

References 1 publication

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“…The effect of width quantization becomes even more critical for circuits like SRAMs and flip-flops in which transistor sizing has a significant effect on the circuit functionality [12]. Conflicting requirements for transistor sizes for stable read and write operations in SRAMs further aggravates the challenge posed by width quantization.…”

Section: Fundamentals Of Finfetsmentioning

confidence: 99%

Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

Gupta

Roy

2014

Circuit Design for Reliability

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FinFETs have emerged as alternatives to conventional bulk MOSFETs in scaled technologies due to superior gate control of the channel, lower short channel effects and higher scalability. However, width quantization in FinFETs constrains the design space of FinFET-based circuits, especially SRAMs in which transistor sizing is critical for the circuit robustness. The adverse effects of width quantization can be mitigated by appropriate device-circuit co-design of FinFETbased memories. This chapter describes some of such techniques with an emphasis on the device-circuit interactions associated with each methodology. The impact of different technology options in FinFETs like gate-underlap, fin orientation, fin height, gate workfunction and independent control of the gates on the stability, power and performance of 6 T SRAMs is discussed.

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Section: Fundamentals Of Finfetsmentioning

confidence: 99%

Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

Gupta

Roy

2014

Circuit Design for Reliability

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“…Meanwhile, a FinFET transistor shows drawbacks in conventional design-techniques. The quantized transistor-width limits a flexible bitcell design in a conventional way [1], [11]. Therefore, it reduces a design space and increases the failure probabilities with the un-optimized bitcell sizing [1], [12].…”

Section: Introductionmentioning

confidence: 99%

A 14 nm FinFET 128 Mb SRAM With V<formula formulatype="inline"> <tex Notation="TeX">$_{\rm MIN}$</tex></formula> Enhancement Techniques for Low-Power Applications

Song

Rim

Jung

et al. 2015

IEEE J. Solid-State Circuits

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Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 m and a 0.080 m 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 with 200 mV improvement by NBL, and 0.47 for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

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“…However, the channel width of the FinFET (fin FET) cannot be controlled as conveniently as that of the planar bulk CMOS transistors. The fin width and height is limited by the aspect ratio, which must be followed [20] to retain its superior electrostatic properties and robustness over the planar devices. In addition, the channel width of the FinFET is quantized.…”

Section: Read Operationmentioning

confidence: 99%

Applications in Static Random Access Memory (SRAM)

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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Continuous efforts to shrink the physical size of transistors enable the integration of a larger number of transistors on a single chip. Today, it is feasible to fabricate a single SRAM cell in a 0.04999-µm 2 area [1]. However, as the transistors are aggressively scaled down, the impacts of the process-induced random variations on the device performance are dramatically increased [2]. The term "process-induced random variations" indicates that the process/fabrication steps such as doping, lithography, etching, chemical mechanical polishing (CMP), and so on, induce these random variations [3]. The well-known random variation sources caused by the aforementioned process steps are random dopant fluctuations (RDF) [4] [also known as random dopant distributions (RDD)] [5], line edge roughness (LER) [6], work function variations (WFV) [7] (also known as metal grain granularity (MGG) [8]), and oxide thickness variations [9]. Aforementioned random variations cause variations in parameters such as effective channel length and threshold voltage of each transistor. Then, the mismatches in the effective channel lengths and threshold voltages between two neighboring transistors cause degradations in the stability of the SRAM cells, which consist of a few transistors (e.g., 6 transistors for 6T SRAM cell) [10]. This is because each transistor of a single SRAM cell should be balanced in order to make it stable for the read/write/retention operations [11]. Further detailed information about how to balance the different transistors of a single SRAM cell, and how badly the stabilities of the SRAM cells are degraded by process-induced variations, will be provided later.Since random variations significantly affect the performance of SRAM cells, it is irrefutable that random variations are one of the key factors in the SRAM cell design. Furthermore, it is important to look for "random variation"-tolerant SRAM designs because random variations cannot be controlled, as systematic variations are controlled [12]. In order to find the random-variation-tolerant SRAM cell designs, understanding how the SRAM cell operates and how the process-induced

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FinFET technology for future microprocessors

Cited by 19 publications

References 1 publication

Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

A 14 nm FinFET 128 Mb SRAM With V<formula formulatype="inline"> <tex Notation="TeX">$_{\rm MIN}$</tex></formula> Enhancement Techniques for Low-Power Applications

Applications in Static Random Access Memory (SRAM)

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