Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

Gupta, Sumeet Kumar; Roy, Kaushik

doi:10.1007/978-1-4614-4078-9_11

Cited by 27 publications

(6 citation statements)

References 28 publications

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“…The simulation study outcome was evaluated with respect to power and delay mainly for both read / write operation. Similar trend of study on 6T SRAM was also carried out by Gupta and Roy [24]. Same year (i.e.…”

Section: Existing Techniquessupporting

confidence: 69%

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Girish¹,

Shashikumar²

2016

CAE

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With the advancement in the energy efficient storage system, FinFET has already gained a pace in the area of computational memory management. However, after reviewing the research work focusing on FinFET based SRAM cells till date, we found that amount of research work towards enhancement of the design principle has not been much in number. Hence, we study some of the recently introduced research contribution towards enhancing the design performance of FinFET based SRAM cells and found that majority of the technique have both advantages and limitations too. We also highlights the significant research gap from the existing studies in order to assist the readers aware of the practicality of the research progress in this regards.

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Section: Existing Techniquessupporting

confidence: 69%

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Girish¹,

Shashikumar²

2016

CAE

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“…The schematic of the tri‐gate FinFET is shown in Figure 1. The ON current of FinFET can be expressed by the following 23 :

I_{O N} = k N_{F i n} \frac{2 H_{F i n} + T_{S i}}{L_{g}} {((), V_{G S} - V_{T})}^{α},

where k is a fitting constant parameter, α is the velocity saturation index, V GS is the gate‐source voltage, V T is the device threshold voltage, N Fin is the number of fins, and H Fin and T Si are the height and thickness of the fins, respectively, which are assumed to be constant due to fabrication related issues.…”

Section: Backgroundsmentioning

confidence: 99%

“…21,22 The schematic of the tri-gate FinFET is shown in Figure 1. The ON current of FinFET can be expressed by the following 23 :…”

Section: Finfet Technologymentioning

confidence: 99%

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Jooq

Ahmadinejad

Moaiyeri

2020

Circuit Theory & Apps

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SummaryThis study proposes two ultraefficient imprecise multipliers based on innovative 4:2 approximate compressor designs. The first proposed multiplier employs an ultracompact 8‐transistor 4:2 compressor to reduce the transistor count and energy dissipation. To improve the accuracy of the first proposed imprecise multiplier, the second multiplier also benefits from a semiaccurate 24‐transistor 4:2 approximate compressor for the high‐order bits. The 7‐nm fin field‐effect transistor (FinFET) technology, as one of the leading commercial technologies, is utilized to simulate the proposed multipliers in the environment. The simulation results indicate that the proposed imprecise multipliers show significant improvements regarding transistor count, delay, power, and power‐delay product as compared to their state‐of‐the‐art imprecise and exact counterparts. Along with the superior hardware efficiency, the MATLAB simulations demonstrate that the proposed multipliers also provide reasonable levels of accuracy. Moreover, a figure of merit (FOM) considering hardware efficiency and output quality is considered in order to evaluate the multipliers comprehensively. The FOM simulation results indicate that the proposed imprecise multipliers make a significant trade‐off between hardware efficiency and quality for approximate‐computing applications dealing with image multiplication.

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“…This lower supply voltage brings many problems in SRAM 5 . Several SRAMs have been proposed with the goal for reducing power and enhancing read static noise margin (RSNM) by decoupling the path from storage node 6–10 …”

Section: Introductionmentioning

confidence: 99%

Half‐selection disturbance free 8T low leakage SRAM cell

Lorenzo

Paily

2022

Circuit Theory & Apps

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Summary This work presents a robust and low leakage new 8T static random access memory (SRAM) cell without any half‐selection disturbance. The proposed cell removes write disturbance by eliminating the trail from supply and ground. Furthermore, it removes the read disturbance by separating the read trail from the storage node. The proposed cell addresses the challenge of half select by using different control signals. The cell achieves low leakage because of virtual ground (VGND), series connected tail transistor, and access series stack transistors. To study the usefulness of the proposed SRAM, it is compared with 6T, 10T, 9T, PG9T, 7T, and 8T SRAM cells. The proposed SRAM minimizes leakage power, write power, and read power by 12.4%, 21.62%, and 29.06%. Furthermore, the proposed cell improves read and write noise margin by 57.19% and 19.96%, respectively, as compared to a conventional 6T SRAM. Again, the write energy consumption lowers to about 43.86× while read energy consumption 28.95× as compared to 10T SRAM.

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Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

Cited by 27 publications

References 28 publications

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Half‐selection disturbance free 8T low leakage SRAM cell

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