FinFETs: from devices to architectures

Bhattacharya, Debajit; Jha, Niraj K.

doi:10.1017/cbo9781316156148.003

Cited by 42 publications

(40 citation statements)

References 83 publications

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“…In contrast, FinFET devices with taller fins offer less flexibility with sizing but have a smaller silicon footprint and the increasing fin heights for successive FinFET nodes combines with the lateral scaling to actually accelerate "Moore's Law"-style scaling; but this might also result in larger short-channel effects and some structural instabilities. 1,8 In addition, taller devices could also lead to an increase in unwanted capacitance. This indicates that there are some opportunities for devicecircuit codesign that are unlikely to become available for fabless companies but could become important for vertically-integrated companies that have their own fabs.…”

Section: Finfet Device Scaling-fin Heightmentioning

confidence: 99%

“…To solve this problem, gate oxides were aggressively thinned and high-k dielectric gate materials were adopted to increase the gate-channel capacitance, but the gate-related issues, such as gate leakage and gate-induced drain leakage (GIDL) increased. 1,2 FinFET devices became attractive for sub-30 nm nodes 3,4 because of their unique channel structure with good gate control that enables a much improved short channel control, thus requiring little or no doping in the channel. The threshold voltage V t can be scaled down in FinFETs for both improved device performance and a much lower operation voltage.…”

Section: Introductionmentioning

confidence: 99%

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Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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It has been almost a decade since FinFET devices were introduced to full production; they allowed scaling below 20 nm, thus helping to extend Moore's law by a precious decade with another decade likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique structure, these 3-D transistors offer significant performance improvements and power reduction compared to planar CMOS devices. As we are entering into the sub-10 nm era, FinFETs have become dominant in most of the high-end products; as the transition from planar to FinFET technologies is still ongoing, it is important for digital circuit designers to understand the challenges and opportunities brought in by the new technology characteristics. In this paper, we study these aspects from the device to the circuit level, and we make detailed comparisons across multiple technology nodes ranging from conventional bulk to advanced planar technology nodes such as Fully Depleted Silicon-on-Insulator (FDSOI), to FinFETs. In the simulations we used both state-of-art industry-standard models for current nodes, and also predictive models for future nodes. Our study shows that besides the performance and power benefits, FinFET devices show significant reduction of short-channel effects and extremely low leakage, and many of the electrical characteristics are close to ideal as in old long-channel technology nodes; FinFETs seem to have put scaling back on track! However, the combination of the new device structures, double/multi-patterning, many more complex rules, and unique thermal/reliability behaviors are creating new technical challenges. Moving forward, FinFETs still offer a bright future and are an indispensable technology for a wide range of applications from high-end performance-critical computing to energy-constraint mobile applications and smart Internet-of-Things (IoT) devices.

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Section: Finfet Device Scaling-fin Heightmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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“…This multi‐gate FET is termed as fin field‐effect transistor (FinFET). FinFET has higher carrier mobility, lesser wafer area, faster‐switching speed, and higher transconductance in comparison with CMOS technology …”

Section: Introductionmentioning

confidence: 99%

FDSTDL: Low‐power technique for FinFET domino circuits

Garg

Gupta

2019

Circuit Theory & Apps

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Summary Major issues in designing low‐power high‐speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field‐effect transistor (FinFET) technology for the design of low‐power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal‐oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2‐, 4‐, 8‐, and 16‐input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK‐DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse‐mesh finite difference (CMFD) technique at a frequency of 200 MHz.

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“…Over the years, the continuous downscaling of device dimensions, has degraded the performance of MOSFETs which lead to various short channel effects (SCEs) like high subthreshold swing (SS), high drain-induced barrier lowering (DIBL) and threshold voltage (V T ) roll-off (Bhattacharya and Jha, 2014;Roy et al, 2003). The scaling of oxide thickness results in gate induced drain leakage (GIDL) (Orouji and Rahimian, 2012;Yeo et al, 2003).…”

Section: Introductionmentioning

confidence: 99%

“…To overcome these problems researcher have proposed various device architectures. Among different device structure, FinFET is a promising candidate, as it can control the channel from all the three side of the gate (Bhattacharya and Jha, 2014;Fasarakis et al, 2012). A MOSFET with Si fin as a vertical channel is named as FinFET.…”

Section: Introductionmentioning

confidence: 99%

GaAs SOI FinFET: impact of gate dielectric on electrical parameters and application as digital inverter

Saha¹,

Bhowmick²,

Baishya³

2018

IJNP

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In this paper, a GaAs SOI (silicon on insulator) FinFET is proposed. A comparative study between proposed GaAs FinFET and conventional Si FinFET is presented. The effects of dielectric constant (k) of gate dielectric material on electrical parameters like channel potential, drain current, and I on /I off have been reported. Results show that as k raises, both I on /I off and channel potential increases. Again the impact of k on short channel effects (SCEs) has been investigated. TCAD results show that as k increases subthreshold swing (SS) improves, drain induced barrier lowering (DIBL) degrades, and V T roll off occur. The impacts of k on gate capacitance (C GG) and intrinsic delay (τ) have been presented and they increases as k increases. A digital CMOS inverter is implemented through proposed FinFET and the effect of k on its delay parameter is estimated. Results shows that average delay increase as k increases.

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FinFETs: from devices to architectures

Cited by 42 publications

References 83 publications

Back to the Future: Digital Circuit Design in the FinFET Era

Back to the Future: Digital Circuit Design in the FinFET Era

FDSTDL: Low‐power technique for FinFET domino circuits

GaAs SOI FinFET: impact of gate dielectric on electrical parameters and application as digital inverter

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