Finite element analysis of substrate warpage during die attach process

Beh, Keh Shin; Ourdjini, Ali; Venkatesh, V.C.; Khong, Y. L.

doi:10.1109/emap.2002.1188819

“…In order to understand the behavior of flip chip packages under thermal loading, numerous numerical and theoretical methods have been employed. For finite element analysis, two-dimensional and three dimensional finite element models have been constructed to study packaging deformation [1], interfacial stresses [2], solder joint shapes and stresses [3], and underfill behaviors and stresses [4] to determine the reliability of packages [5]. Parametric studies have also been presented to determine the optimal properties and dimensions of the materials and devices in packages [1][2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Mechanical behavior of flip chip packages under thermal loading

Wua¹,

Chena²,

Tsaia³

et al.

Proceedings Electronic Components and Technology, 2005. ECTC '05.

3

0

View full text Add to dashboard Cite

Concern on stresses in solder bumps/underfill and warpage of flip chip BGA packages increases recently because reliability of flip chip packages relates directly to the corresponding stresses and warpage. In addition, when die size increases, the problem becomes more annoying. This problem is mainly due to mismatch in the coefficient of thermal expansion (CTE) and Young's modulus for materials made of substrate, silicon chip, underfill, and solder joints. In this paper, CTE for BT substrates were measured using electronic speckle pattern interferometry (ESPI) in different manufacturing stages to understand the effect of via drilling, Cu plating and patterning, and solder mask coating. The effect due to solder mask coating on CTE change was found to the most significant. Further, the CTE of BT substrates used in wire bond BGA packages and flip chip BGA packages varied significantly due to use of different core materials and different thickness of solder mask. On warpage measurement, 40x40 mm FCBGA with die size equal to 10x10, 20x20, and 26x26mm and thickness equal to 730 and 400um were employed and the measurement was performed from room temperature up to 225 o C. The phase-shifted shadow moiré technique was adopted for this warpage measurement. 2D and 3D finite element models were also constructed to analyze the warpage and stresses of these FC BGA packages. It was found that with accurate CTE data of the substrate as the input the predicted warpage was in excellent agreement with the experimental data, which made it possible to perform meaningful parametric analyses and optimal design of large-sized FC BGA packages.

show abstract

“…For finite element analysis, two-dimensional and three dimensional finite element models have been constructed to study packaging deformation [1], interfacial stresses [2], solder joint shapes and stresses [3], and underfill behaviors and stresses [4] to determine the reliability of packages [5]. Parametric studies have also been presented to determine the optimal properties and dimensions of the materials and devices in packages [1][2][3][4][5][6]. On the other hand, experimental tools have been adopted to directly measure the behavior of flip chip packages at different temperatures.…”

Section: Introductionmentioning

confidence: 99%

Mechanical Behavior of Flip Chip Packages under Thermal Loading

Chen

¹

,

Tsai

²

,

Kao

³

et al.

Micro- And Opto-Electronic Materials and Structures: Physics, Mechanics, Design, Reliability, Packaging

2

0

View full text Add to dashboard Cite

Concern on stresses in solder bumps/underfill and warpage of flip chip BGA packages increases recently because reliability of flip chip packages relates directly to the corresponding stresses and warpage. In addition, when die size increases, the problem becomes more annoying. This problem is mainly due to mismatch in the coefficient of thermal expansion (CTE) and Young's modulus for materials made of substrate, silicon chip, underfill, and solder joints. In this paper, CTE for BT substrates were measured using electronic speckle pattern interferometry (ESPI) in different manufacturing stages to understand the effect of via drilling, Cu plating and patterning, and solder mask coating. The effect due to solder mask coating on CTE change was found to the most significant. Further, the CTE of BT substrates used in wire bond BGA packages and flip chip BGA packages varied significantly due to use of different core materials and different thickness of solder mask. On warpage measurement, 40x40 mm FCBGA with die size equal to 10x10, 20x20, and 26x26mm and thickness equal to 730 and 400um were employed and the measurement was performed from room temperature up to 225 o C. The phase-shifted shadow moiré technique was adopted for this warpage measurement. 2D and 3D finite element models were also constructed to analyze the warpage and stresses of these FC BGA packages. It was found that with accurate CTE data of the substrate as the input the predicted warpage was in excellent agreement with the experimental data, which made it possible to perform meaningful parametric analyses and optimal design of large-sized FC BGA packages.

show abstract