Abstract:A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are checked independently. By checking parity on the present state instead of the next state, this technique allows detection of errors in bistable elements (that were hitherto not detected by many previous techniques) while requiring no changes in the original machine specifications. This paper also examines design choices with respect … Show more
“…Техническое состояние функционирующего дискретного устройства (без отключения от управляемых объектов) позволяет контролировать самопроверяемые схемы встроенного контроля (ССВК) [11][12][13][14]. При организации систем функционального контроля также используют избыточные коды, ориентированные на обнаружение ошибок [15,16].…”
“…Техническое состояние функционирующего дискретного устройства (без отключения от управляемых объектов) позволяет контролировать самопроверяемые схемы встроенного контроля (ССВК) [11][12][13][14]. При организации систем функционального контроля также используют избыточные коды, ориентированные на обнаружение ошибок [15,16].…”
“…In particular, a self-checking FSM, synthesized like in [7], has been mapped in the FPGA contained in the SoC. The control of the outputs correctness is achieved by using parity based code.…”
Section: Fault Detection and Fault Coverage Strategymentioning
confidence: 99%
“…In the presented methodology, the self-checking property has been obtained by using parity check codes and the FSM (mapped into the FPGA) is synthesized by using the technique presented in [7]. The use of parity check codes means that output correct code words show always the same parity.…”
Section: Fault Detection Using Parity Check Codesmentioning
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