FIR filter design program that matches specifications rather than filter coefficients results in large savings in FPGA resources

Tan, Kah-Howe; Leong, Wen Fung; Kaluri, K.; Soderstrand, M.A.; Johnson, L.G.

doi:10.1109/acssc.2001.987711

Cited by 8 publications

(1 citation statement)

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“…With the development of programmable logic devices and EDA technologies, FPGA can meet the needs of miniaturization of electronic systems [1][2][3][4][5][6] , low-power, high-reliability, and short development cycle, low software development investment, and lower and lower chip prices, therefore FPGA is more and more chosen by the market, especially applied in low-volume, multispecies products. And the FPGA devices are of hardware parallel organization, and the parallel iterative algorithm of digital filters is very suitable for FPGA to achieve.…”

Section: Introductionmentioning

confidence: 99%

Design of a High-Speed Digital FIR Filter Based on FPGA

2012

AMR

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To realize filtering of high-speed input data, and aiming at the design method of systolic FIR digital filter, this paper proposes a design method of high-speed FIR filter based on FPGA. The states conversion between coefficients configuring mode and filtering mode is finished by FSM (Finite State Machine), which ensures the system to work orderly. The experimental results demonstrated, it can reduce the input dimension and eliminate linear and nonlinear interference effectively. In addition, it is very suitable for hardware implementation due to its simple structure.

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