First Demonstration of an All Analog Adaptive Equalizer for Coherent DP-QPSK Links

Nambath, Nandakumar; Anghan, Mehul; Thaker, Nandish Bharat; Ashok, Rakesh; Kamran, Rashmi; Mishra, Arvind Kumar; Gupta, Shalabh

doi:10.1364/ofc.2017.m3d.5

Cited by 11 publications

(5 citation statements)

References 7 publications

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“…Similar constellations are obtained for the Y polarization also. Preliminary measurement results of the equalizer at a lower data rate were presented earlier in [28].…”

Section: A Measurement Results At 40 Gb/s Data Ratementioning

confidence: 99%

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All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

Nambath

Ashok

Manikandan

et al. 2020

J. Lightwave Technol.

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We present the detailed architecture of an allanalog adaptive equalizer for low-power analog signal processing based coherent optical dual-polarization quadrature phase-shift keying transceivers. The proof of concept equalizer uses the constant modulus algorithm for weight coefficient update. The equalizer, implemented in a 130 nm SiGe BiCMOS technology for 100 Gb/s operation, occupies ∼1.4 mm × 1.35 mm area and draws 1 A current from a 2.5 V supply. Its functionality is validated experimentally for data rates up to 40 Gb/s and by using postlayout circuit simulations for data rates up to 100 Gb/s. The equalizer output after processing with a behavioral Costas loopbased carrier phase recovery and compensation module shows bit error rates well within the hard-decision forward error correction limit for 40 Gb/s single-mode fiber links of length up to 10 km. Performance and power consumption of the equalizer are expected to improve when implemented in advanced CMOS or FinFET technologies. The simple architecture of the analog domain equalizer makes it suitable for analog coherent shortreach interconnects with length less than 10 km and carrier wavelengths of either 1310 nm or 1550 nm.

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“…Similar constellations are obtained for the Y polarization also. Preliminary measurement results of the equalizer at a lower data rate were presented earlier in [28].…”

Section: A Measurement Results At 40 Gb/s Data Ratementioning

confidence: 99%

“…However, the first all-analog adaptive equalizer for DP-QPSK coherent optical system that uses a CMA algorithm for weight coefficient update was demonstrated in our previous work [28]. In this paper, we report the proof-of-concept demonstration of the equalizer operating at a rate as high as 40 Gb/s.…”

Section: Introductionmentioning

confidence: 95%

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

Nambath

Ashok

Manikandan

et al. 2020

J. Lightwave Technol.

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“…In the future, continuous time adaptation systems for the equalizer taps can be implemented on chip to perform iterative updates. In [6], a possible implementation using a constant modulus algorithm is proposed and tested in [7] to obtain an 8 Gb/s analog coherent link. Updates can also be guided by using binary information coming from extra data slicers in the decoder as mentioned in [11].…”

Section: System Experimentsmentioning

confidence: 99%

“…Conventional DSP solutions require accurate high speed ADCs. State-of-the art reported ADC designs are presented in [3] and [4] consuming respectively 0.95 and 0.7 W. To avoid these consuming ADCs, several solutions are introduced in [1], [5]- [7] and [8] to create 'Coherent-lite' transceivers. These systems try to take advantage of a limited amount of channel impairments to either reduce/simplify the amount of DSP [8] or remove it [1] [6] by moving crucial signal processing steps to the analog domain.…”

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confidence: 99%

Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

Verplaetse

Lambrecht

Vanhoecke

et al. 2020

IEEE J. Solid-State Circuits

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We propose a novel implementation of a complex analog equalization filter for the compensation of frequency dependent variations in coherent optical links. The analog compensation filter can be used in coherent-lite optical communication links where digital signal processing (DSP) is removed to limit the complexity and power consumption. In these links, the filter can compensate electrical bandwidth limitations and distortion introduced by chromatic dispersion in the fiber. The complex filter is implemented by combining 4 distributed analog finite impulse response (FIR) filters to obtain the necessary response. The filter delays are implemented using active delay cell structures to create a compact solution. The analog filter is implemented in a 55nm BiCMOS technology and consumes 185 mW core power for 5 complex filter taps. Performance is evaluated using S-parameter measurements, noise and linearity measurements and real-time system experiments using 112 Gb/s 16-QAM modulated signals.

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“…The equalizer based on a blind CMA algorithm can be considered optimal for phase modulated signals. The analogdomain CMA equalizer which is designed for DP-QPSK systems [9] is used with the SH-QPSK system. The equalizer has feed forward taps for X and Y polarization signals as well as cross taps between both the polarization signals, as presented in Fig.…”

Section: All Analog Domain (Dsp-free) Equalizermentioning

confidence: 99%

Demonstration of a low-power, local-oscillator-less, and DSP-free coherent receiver for data center interconnects

et al. 2020

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We present the first demonstration of a local oscillator (LO)-less digital signal processing (DSP)-free coherent receiver for high-capacity short distance optical links. Experimental results with an analog domain constant modulous algorithm (CMA)-based equalizer chip for the self-homodyne quadrature phase shift keying (SH-QPSK) system validate the employability of an all-analog and LO-less receiver for low-power interconnects.

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First Demonstration of an All Analog Adaptive Equalizer for Coherent DP-QPSK Links

Cited by 11 publications

References 7 publications

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

Demonstration of a low-power, local-oscillator-less, and DSP-free coherent receiver for data center interconnects

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