First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

Subramanian, Sharath; Hosseini, Motaharesadat; Chiarella, T.; Sarkar, Santonu; Schuddinck, P.; Chan, Boon Teik; Radisic, Dunja; Mannaert, G.; Hikavyy, Andriy; Rosseel, Erik; Sebaai, Farid; Peter, A.; Hopf, T.; Morin, P.; Wang, S.; Devriendt, K.; Batuk, Dmitry; Martinez, G.T.; Veloso, A.; Litta, E. Dentoni; Baudot, S.; Siew, Yong Kong; Zhou, Xiaoxin; Briggs, B.; Capogreco, E.; Hung, Jaclyn Y.; Koret, Roy; Spessot, A.; Ryckaert, Julien; Demuynck, S.; Horiguchi, N.; Boemmels, J.

doi:10.1109/vlsitechnology18217.2020.9265073

Cited by 63 publications

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“…The device TCAD model was designed and calibrated based on the world's first reported monolithic CFET device [3], and was scaled to the 3-nm node specifications proposed by the IRDS [22]. The detailed model parameters are listed in Table I.…”

Section: Design and Simulation Methodologymentioning

confidence: 99%

“…The design was based on the idea that it is possible for the transistors in a CMOS logic cell to share a common gate structure. IMEC proposed the process flow for the world's first monolithic CFET device in 2018, and demonstrated it in cell array form appropriate for mass fabrication in 2020 [1]- [3]. NARLabs demonstrated the first CMOS inverters and 6-T SRAM cells using CFET devices with junctionless transistors in 2019 [4], and Intel demonstrated CFET devices incorporating a novel dual metal gate process in 2020 [5].…”

Section: Introductionmentioning

confidence: 99%

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Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

et al. 2021

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For the first time, the electrothermal characteristics of a three-dimensional (3D) monolithic complementary FET (CFET) in DC operation as well as in AC CMOS operation were investigated with TCAD simulations. The self-heating effect (SHE) in a monolithic CFET is expected to be a critical problem given its highly compact architecture. DC analysis of the individual NFET and PFET devices revealed that increasing the channel width from 5.0 to 7.0 nm improved the thermal resistance up to 8.5% and the RC delay up to 9.6%, while greatly deteriorating the on/off ratio. AC CMOS inverter simulations of the CFET showed that reducing the NFET/PFET vertical separation from 30 to 10 nm resulted in 11.9% faster operation frequency and 3.4% reduced dynamic power loss, but 11.2% higher rise in device temperature. The clear trade-off relationships between the thermal and electrical performance factors necessitate optimization of the device dimension parameters. These findings are expected to provide critical insight for the design technology co-optimization (DTCO) in the 3-nm regime.INDEX TERMS Complementary FET (CFET), self-heating effect (SHE), 3D monolithic integration, TCAD, thermal resistance, time delay, figure of merit (FoM), CMOS inverter, device optimization.

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Section: Design and Simulation Methodologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

et al. 2021

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“…The theoretical simulation results demonstrate that carbon nanotube-based monolithic three-dimensional integrated circuits have 1000 times performance and power consumption advantages over the traditional integrated circuits. Combined with the feature mentioned above that carbon nanotube can be used to construct a variety of functional devices, it is conducive to realizing the integration of sensing, memory, and computing chip in three-dimensional architecture just like the structure shown in Figure 15 [75][76][77][78][79][80][81].…”

Section: Challenge and Outlookmentioning

confidence: 99%

Carbon nanotube-based CMOS transistors and integrated circuits

Xie

Zhang

2021

Sci. China Inf. Sci.

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Over the last sixty years, the scaling of silicon-based complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have promoted the rapid development of microelectronic technology. However, the development of Si CMOS technology is currently subject to serious challenges from various aspects such as physics limit, cost, and power consumption, and is becoming increasingly difficult. Material innovation is exerting an ever-greater role in the integrated circuit design. By looking for thinner semiconductor materials with higher mobility as the active layer to construct smaller and higher-performance transistors, it is possible to further stimulate transistors and integrated circuits on performance, density, power dissipation, and functions. In 1991, Iijima discovered carbon nanotubes (CNTs). Due to its excellent electrical properties and intrinsic nano-scale size, CNT has been considered by academia and industry to have great potential to replace silicon materials in the future for the extremely scaled technology nodes or novel electronic applications. This paper reviews the latest advancements in CNT-based electronics research. Finally, the challenges and pathways for nanotube transistors to transition into commercial applications are discussed.

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“…Gate-all-around nanowire (NW) and nanosheet FETs have also been introduced to enhance the gate electrostatics and current drivability [2]. Also, designtechnology co-optimization including complementary FET [3]- [5] and buried power rail (BPR) [6] enables further technology node scaling in terms of front-end-and back-endof-lines. Middle-of-line (MOL) schemes such as self-aligned contact and contact-over-active-gate contact increases the device density by placing metal contacts within the active layout region [7].…”

Section: Introductionmentioning

confidence: 99%

“…Cox is oxide capacitance, Vgs is gate-source voltage, and Vth is threshold voltage. According to the eqs (3). and(4), Gm/Ids is given by 1/(Vgs -Vth).…”

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confidence: 99%

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

et al. 2021

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Vertical nanowire field-effect transistors (NWFETs) have been optimized to maximize digital and analog performances using fully-calibrated TCAD and machine learning (ML) technique. Digital performance is quantified by RC delay (CggVdd/Ion, where Cgg is gate capacitance, Vdd is operation voltage, and Ion is on-state current) at the fixed off-state currents, and analog performance is quantified by the product of cutoff frequency (Ft) and transconductance efficiency (Gm/Ids). ML accurately predicted the geometry and doping parameters suggesting the best device performances. All the optimized NWFETs have larger drain diameters but smaller source diameters at the minimum of gate lengths, gate oxide thicknesses, drain junction gradients, and source/drain spacer lengths. Small source diameters are needed to tightly control the energy barrier to reduce the short-channel effects, whereas large drain diameters increase current drivability than Cgg. Small drain junction gradients increase the lateral electric field from source to drain, which increases the carrier velocity. Longer spacer lengths decrease both Ion and Cgg, but the Ion degradation is critical. These device characteristics validate the optimization results from ML, and ML-based optimization is fast and effective to maximize both digital and analog performances.

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First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

Cited by 63 publications

References 0 publications

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Carbon nanotube-based CMOS transistors and integrated circuits

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

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