First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration

Zeng, A.; Lü, Jian–Qiang; Rose, K.; Gutmann, R.J.

doi:10.1109/mdt.2005.138

Cited by 44 publications

(14 citation statements)

References 9 publications

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“…Besides the benefits of interconnect performance [5,6], this scheme leads to increased transistor packing density, smaller chip area, lower power dissipation, and provides means to integrate dissimilar technologies (digital, analog, RF circuits, etc) in the same chip, but on different active layers. Alongside research into developing processing technology for 3-D ICs [5,7], several works in the literature have explored possible applications for this revolutionary technology [5,7,8,9]. One of the most promising applications is that of integrating a processor-andmemory system on a single 3-D chip.…”

Section: Introductionmentioning

confidence: 99%

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

Loi¹,

Agrawal²,

Srivastava³

et al. 2006

2006 43rd ACM/IEEE Design Automation Conference

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Section: Introductionmentioning

confidence: 99%

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

Loi¹,

Agrawal²,

Srivastava³

et al. 2006

2006 43rd ACM/IEEE Design Automation Conference

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“…The method of using Elmore delay model is suitable to estimate interconnect performance at the early stages of design flow where all the TABLE IV ARCHITECTURE CONFIGURATIONS FOR GRAPHITE SIMULATOR TABLE V BENCHMARK PROGRAMS IN THREE TEST PROGRAM SUITS logics are not synthesized yet, because the design tools for the TSV and the 3-D technology we used are not publicly available. The same method was already used and verified in [66] and [75] for estimating interconnect performance of 3-D ICs. Especially in [75], delay estimation using the firstorder Elmore model for 3-D cache memory has been validated by the Cadence Spectre [76] simulation of a four-way 18-Mb Intel SRAM cache at the 180-nm technology node, achieving an accuracy within 10% of the Cadence simulation result.…”

Section: Methodsmentioning

confidence: 99%

“…The same method was already used and verified in [66] and [75] for estimating interconnect performance of 3-D ICs. Especially in [75], delay estimation using the firstorder Elmore model for 3-D cache memory has been validated by the Cadence Spectre [76] simulation of a four-way 18-Mb Intel SRAM cache at the 180-nm technology node, achieving an accuracy within 10% of the Cadence simulation result. To estimate interconnect power, we used analytical models proposed in [77].…”

Section: Methodsmentioning

confidence: 99%

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Kang

Benini

Micheli

2015

IEEE Trans. VLSI Syst.

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Abstract-3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and lowlatency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect [6] that is straightforwardly adapted to 3-D integration, the proposed method yields up to ×2.11 and ×1.11 improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu-Cu TSV bonding techniques, respectively. Index Terms-3-D integration, multicore, networks-on-chip (NoC), scratchpad memory (SPM).

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“…Many different uses of 3-D integration have been proposed, from stacking additional memory or extra levels of cache [10,34,43,24,47,20,19] to stacking multiple processors [6]. These two examples exploit the full advantages of 3-D chips, as attaching additional memory can provide lower latency compared to off-chip memory, and power can be saved because driving TSVs requires less power than long off-chip wires.…”

Section: Applications Of 3-d Integrationmentioning

confidence: 99%

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

Valamehr

Huffmire

Irvine

et al. 2012

Cryptography and Security: From Theory to Applications

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3-D integration presents many new opportunities for architects and embedded systems designers. However, 3-D integration has not yet been explored by the cryptographic hardware community. Traditionally, crypto coprocessors have been implemented as a separate die or by utilizing one or more cores in a chip multiprocessor. These methods have their drawbacks and limitations in terms of tamper-resistance, side-channel immunity and performance. In this work we propose a new class of co-processors that are "snapped-on" to the main processor using 3-D integration, and we investigate their security ramifications. These 3-D co-processors hold many advantages over previous implementations. This paper begins with an overview of 3-D integration and its prior applications. We then outline security threat models relevant to crypto co-processors and discuss the advantages and disadvantages of using a dedicated 3-D crypto co-processor compared to traditional, commodity, off-chip crypto co-processors. We also discuss the performance improvements that can be gained from using a 3-D approach.

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First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration

Cited by 44 publications

References 9 publications

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

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