A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

Loi, G.L.; Agrawal, B.; Srivastava, N.; Lin, Sung-Chyr; Sherwood, T.; Banerjee, K.

doi:10.1109/dac.2006.229426

Cited by 45 publications

(66 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We will show that by considering more memory controllers as well as aggressive operating frequencies, the speedup offered by 3D integration becomes much greater as long as the associated heat dissipation can be managed via micro-fluidic cooling. The work by Loi et al has demonstrated that memory bound programs can get performance improvements of 3x or more by stacking DRAM on logic, but that for CPU bound programs, degradation actually occurs by going to a 3D implementation due to temperature increases [11]. These results are consistent with our finding, which is that 3D integration can only offer performance increases when sufficient cooling is applied to the chip.…”

Section: Previous Worksupporting

confidence: 94%

High performance 3D stacked DRAM processor architectures with micro-fluidic cooling

Serafy

Shi

Srivastava

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

View full text Add to dashboard Cite

In this work we consider new 3D IC processor architectures that become feasible only when aggressive cooling is used. In traditional air cooled 3D processors, heat removal is a big issue, and so designers often pursue low performance architectures in order to prevent thermal violations. We attempt to explore the new design space that is available to computer architects when micro-fluidic cooling is applied to the 3D chip. We show that adding more memory controllers to a 3D processor can offer the potential for huge increases in performance, but also drastically increases the temperature of an uncooled chip, making them infeasible. With micro-fluidic cooling, these performance increases become realizable and new high performance architectures can be designed when cooling is co-designed with the architecture. We observe a 2.4x increase in average performance when comparing a 3D stacked memory processor with and without micro-fluidic cooling. This performance increase occurs because the cooling unlocks the possibility of adding more memory controllers as well as more aggressive frequency scaling. Cooling also improves the energy efficiency of the processors since a slight increase in cooling power helps to significantly reduce the leakage levels. This combined with improvements in performance due to aggressive cooling helps to increase energy efficiency on average 16.8x.

show abstract

Section: Previous Worksupporting

confidence: 94%

High performance 3D stacked DRAM processor architectures with micro-fluidic cooling

Serafy

Shi

Srivastava

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

View full text Add to dashboard Cite

show abstract

“…Performance analysis for 3D systems with on-chip DRAM typically focuses on comparing the system performance between 2D and 3D systems. Loi et al show that on-chip memory delivers significant amount of speedup for three SPEC benchmarks [3]. Liu et al report up to 126% speedup for single-core processors with 3D memory stacking [2].…”

Section: Related Workmentioning

confidence: 98%

“…Recently, several research groups have introduced approaches for modeling performance in 3D systems, focusing on a small number of cores (single-core, quad-core) and single-threaded workloads [2], [3], [4]. Thermal hotspots have been a pressing issue due to the cooling costs and reliability challenges in conventional 2D design as well as 3D systems.…”

Section: Introductionmentioning

confidence: 99%

Exploring performance, power, and temperature characteristics of 3D systems with on-chip DRAM

Meng

Rossell

Coskun

2011

2011 International Green Computing Conference and Workshops

View full text Add to dashboard Cite

3D integration enables stacking DRAM layers on processor cores within the same chip. On-chip memory has the potential to dramatically improve performance due to lower memory access latency and higher bandwidth. Higher core performance increases power density, requiring a thorough evaluation of the tradeoff between performance and temperature. This paper presents a comprehensive framework for exploring the power, performance, and temperature characteristics of 3D systems with on-chip DRAM. Utilizing this framework, we quantify the performance improvement as well as the power and thermal profiles of parallel workloads running on a 16-core 3D system with on-chip DRAM. The 3D system improves application performance by 72.6% on average in comparison to an equivalent 2D chip with off-chip memory. Power consumption per core increases by up to 32.7%. The increase in peak chip temperature, however, is limited to 1.5 o C as the lower power DRAM layers share the heat of the hotter cores. Experimental results show that while DRAM stacking is a promising technique for high-end systems, efficient thermal management strategies are needed in embedded systems with cost or space restrictions to compensate for the lack of efficient cooling.

show abstract

“…For its numerous opportunities, it attracts substantial number of researches from industry and academia of 3D stacking. Bryan et al have evaluated the 3D stacking in terms of power and performance [1], and Loi et al have analyzed the processor-memory hierarchy using 3D technologies for performance and thermal perspectives [2]. Also, Black et al have researched on die stacking 3D microarchitecture made up only SRAM or DRAM [9].…”

Section: Related Workmentioning

confidence: 99%

“…Remarkable strength of 3D integration is additional reduction of area size, wire length, and performance progress. Heterogeneous memory dies in different memory types, such as dynamic random access memory (DRAM), magnetic random access memory (MRAM) and phase change random access memory (PRAM), can be stacked on a microprocessor [1,2].…”

Section: Introductionmentioning

confidence: 99%

Hybrid cache architecture replacing SRAM cache with future memory technology

Lee

Jung

Kyung

2012

2012 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

Recently, hybrid cache architecture has become illuminated. As heterogeneous memory dies are stacked, it improves the performance of microprocessor enhanced in terms of power consumption and processing speed. This paper analyzed the hybrid cache architecture using different programs and memory types. SRAM is fixed for L1 cache memory, whereas DRAM, MRAM, and PRAM are the candidates for L2 cache memory. Each memory structure has the area satisfying the least Average Memory Access Time (AMAT) under a given area condition. Architecture composed of SRAM and MRAM shows 16.9% reduction in average memory access time and 15.2% of power reduction compared with that composed of homogeneous SRAM. Structure of SRAM and DRAM represents 33.0% reduction in power consumption, and that of SRAM and PRAM shows a potential to reduce area and power consumption due to their high density.

show abstract

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

Abstract: ABSTRACT

Cited by 45 publications

References 23 publications

High performance 3D stacked DRAM processor architectures with micro-fluidic cooling

High performance 3D stacked DRAM processor architectures with micro-fluidic cooling

Exploring performance, power, and temperature characteristics of 3D systems with on-chip DRAM

Hybrid cache architecture replacing SRAM cache with future memory technology

Contact Info

Product

Resources

About