Fixed-point error analysis of radix-4 FFT

Prakash, Shamsher; Rao, V.

doi:10.1016/0165-1684(81)90077-3

Cited by 21 publications

(4 citation statements)

References 14 publications

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“…This can be attributed to the less computation stages in Radix-4, which results in less accumulation of arithmetic errors. Our observation matches with the theoretical results in [5]. Note that, Flavor in Table I; QPSK, Gray mapping, n = 1024, r = 1/2, Non-systematic conv.…”

Section: Simulation Results and Observationssupporting

confidence: 94%

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Efficient implementations from libraries: Analyzing the influence of configuration parameters on key performance properties

Ramakrishnan

Jacobsmuehlen

Lai

et al. 2009

2009 IEEE 20th International Symposium on Personal, Indoor and Mobile Radio Communications

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Library based waveform (WF) development approaches have the potential to address one of the key challenges in software defined radio technology, developing portable and at the same time implementation-efficient WFs. The term WF, in this paper, represents a complete wireless standard with several modes. Upon standardizing the library and the interfaces of its components, different vendors can provide Flavors, which are efficient implementations, for some/all components of a WF as a board-support-package. Flavors might provide different trade-offs with respect to key performance related properties like bit error rate, throughput, latency, area, etc. This paper analyzes such a scenario by using FFT as an example. We use 10 Flavors of FFT from 2 vendors for 3 processing elements to analyze the influence of configuration parameters like input data-width, scaling, etc. on the performance properties. Analysis has been performed by doing two tests: using a simple OFDM transceiver system, calculating root mean square error. Based on our analysis, we have identified the main parameters that influence the properties. Our investigations stress the need for modeling the differences in performance on key properties in terms of the influencing parameters. Such a model can assist in selecting a set of appropriate Flavors for implementing a WF and enable tool assisted WF-development. Furthermore, it is evident from our investigations that Flavors exhibit trade-offs in properties and pose tough constraints in several aspects.

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Section: Simulation Results and Observationssupporting

confidence: 94%

“…Performance analysis of FFT has been done by evaluating the error variance in [4][5][6]. Recently, error analysis has been done focussing on few parameters [7] and on few properties, e.g.…”

Section: Motivation: the Nucleus Conceptmentioning

confidence: 99%

Efficient implementations from libraries: Analyzing the influence of configuration parameters on key performance properties

Ramakrishnan

Jacobsmuehlen

Lai

et al. 2009

2009 IEEE 20th International Symposium on Personal, Indoor and Mobile Radio Communications

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“…Floating point representation of data (I/O samples, internal data-paths, twiddle factors) implies too large internal word lengths and is not suitable for ASIC implementation of large transform sizes [10,14]. Assessing the impact of finite-precision arithmetic is thus crucial for configuring the core.…”

Section: Machine Arithmetic Designmentioning

confidence: 99%

“…The proposed IP core is based on radix-4 factorization, because of its higher output precision and reduced number of multiplications with respect to radix-2 factorization [14]. As a drawback, radix-4 factorization is applicable only for power-of-four transform lengths, thus an optional radix-2 stage is required if transform length is a power-of-two.…”

Section: Fft/ifft Configurable Architecturementioning

confidence: 99%

Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems

L'Insalata¹,

Saponara²,

Fanucci³

et al. 2007

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

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This paper presents an environment for the automatic generation of FFT/IFFT cores. The cores are derived from a pipelined cascade architecture template supporting run-time programmable length, transform type selection and three different machine arithmetics (fixed-point, block floating-point and convergent block floating-point). The tool profiles arithmetics and generate the macrocell with the minimum operands bit-width (hence minimum circuit complexity) within the numerical accuracy budget given by the target application. Four case studies illustrate the use of the environment in multi-band OFDM communication systems (WLAN, xDSL, DVB-T/H and UWB). Implementation results of the generated macrocells are evaluated on a 65 nm CMOS standard cells library. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity (gate count, RAM/ROM bits) while keeping the same system level performance (throughput, transform size and numerical accuracy

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