Flash memory disturbances: modeling and test

Mohammad, M.G.; Saluja, Kewal K.

doi:10.1109/vts.2001.923442

Cited by 45 publications

(22 citation statements)

References 7 publications

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“…13 show that, for Df2<200 kΩ, the write operation is not correctly performed. The read operations after the write operation on FGt 11 show that all FG-transistors (except FGt 11 ) are read as containing a logic '1' since they are erased. The read operation on FGt 11 returns a logic '1' for Df2<200 kΩ.…”

Section: Df2 Analysismentioning

confidence: 99%

“…The read operations after the write operation on FGt 11 show that all FG-transistors are read as containing a logic '0'. Consequently, the faulty behavior induced by Df3 is modeled by a SAF0 (Stuck-At Fault 0) of all the FG-transistors.…”

Section: Df3 Analysismentioning

confidence: 99%

“…Figure 17 shows the waveforms of Vt levels and bit-line currents obtained with the proposed model during Op.1 to Op.4. Three FG-transistors are considered: FGt 11 and FGt 12 as defective FT-transistors and FGt 22 elsewhere in the array.…”

Section: Df10 Analysismentioning

confidence: 99%

“…Moreover, the Vt level of FGt 12 increases to reach the level of FGt 11 , thus Df10 induces a non-desired write on FGt 12 . The read operation after the write operation on FGt 11 shows that FGt 11 and FGt 12 are read as containing a logic '0'. It means a write operation on FGt 11 induces a write operation on FGt 12 .…”

Section: Df10 Analysismentioning

confidence: 99%

“…Moreover, as high electric field is required to support its various operation, eFlash may be subject to complex disturbance phenomena [4,6,11].…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

et al. 2012

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The embedded Flash (eFlash) technology can be subject to defects creating functional faults. In this paper, we first generalize the electrical model of the ATMEL TSTAC™ eFlash memory technology proposed in [10]. The model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model is validated by means of simulations and comparisons with ATMEL silicon data. Then, we present a complete analysis of actual resistive defects (open and short) that may affect the ATMEL TSTAC™ eFlash array by considering the proposed model on a hypothetical 4×4 array. This analysis highlights the interest of the proposed model to provide a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing. Responsible Editor: C. A. Papachristou This paper is an extended version of a previously published paper. Main contributions of this paper with respect to [10] are: -A generalization of the model initially proposed in [10] to the case of multiple word-lines, -A complete analysis of actual resistive defects (open and short) that may affect the ATMEL TSTAC/ eFlash array, -A fault modeling of actual resistive defect injection.

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Section: Df2 Analysismentioning

confidence: 99%

Section: Df3 Analysismentioning

confidence: 99%

Section: Df10 Analysismentioning

confidence: 99%

Section: Df10 Analysismentioning

confidence: 99%

“…Moreover, as high electric field is required to support its various operation, eFlash may be subject to complex disturbance phenomena [4,6,11].…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

et al. 2012

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A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash

et al. 2009

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Ethernet controller SoC design and its low-power DFT considerations

Zheng

Zou

2008

Wuhan Univ. J. Nat. Sci.

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In this paper, an Ethernet controller SoC solution and its low power design for testability (DFT) for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit (MCU), media access control (MAC) circuit and embedded memories such as static random access memory (SRAM), read only memory (ROM) and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits: the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test (BIST). By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor (CMOS) technology, the die area is 4.8×4.6 mm 2 . Test results show that the maximum throughput of Ethernet packets may reach 7 Mb s 1 .

show abstract

Flash memory disturbances: modeling and test

Cited by 45 publications

References 7 publications

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash

Ethernet controller SoC design and its low-power DFT considerations

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