Flip-chip integrated silicon photonic bridge chips for sub-picojoule per bit optical links

Thacker, Hiren; Luo, Ying; Shi, Jing; Shubin, Ivan; Lexau, Jon; Zheng, Xuezhe; Li, Guoliang; Yao, Jin; Costa, Joannes M.; Pinguet, Thierry; Mekis, Attila; Dong, Po; Liao, Shirong; Feng, Dazeng; Asghari, Mehdi; Ho, Ron; Raj, Kannan; Mitchell, James G.; Krishnamoorthy, Ashok V.; Cunningham, J. E.

doi:10.1109/ectc.2010.5490965

Cited by 27 publications

(22 citation statements)

References 8 publications

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“…Any epoxy on the grating couplers would degrade output efficiency. As seen on this image, the edge-bead extended less than 20 μm from the VLSI chip edge [20]. Fig.…”

Section: Connecting To the Bridge Chipsmentioning

confidence: 75%

“…To mitigate this, the photonic bridge chips were assembled in diving board geometries, as shown in Fig. 11, such that at least one edge of the photonic chip was sufficiently exposed to provide access for surface-normal or edge-coupling optical I/Os [20]. This same diving board geometry is also used to produce wings for alignment to neighboring island chips in our 4 × 4 array example prototype.…”

Section: Connecting To the Bridge Chipsmentioning

confidence: 99%

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Integration and Packaging of a Macrochip With Silicon Nanophotonic Links

Cunningham

Krishnamoorthy

et al. 2011

IEEE J. Select. Topics Quantum Electron.

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Abstract-The technologies associated with integration and packaging have a significant impact on the overall system. In this paper, we review a silicon photonic "macrochip" system and its associated packaging that will allow dense wavelengthdivision multiplexed optical links to be intimately integrated and co-manufactured with the switching electronics. For this to happen, we anticipate a number of integration and packaging advances.

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“…Any epoxy on the grating couplers would degrade output efficiency. As seen on this image, the edge-bead extended less than 20 μm from the VLSI chip edge [20]. Fig.…”

Section: Connecting To the Bridge Chipsmentioning

confidence: 75%

Section: Connecting To the Bridge Chipsmentioning

confidence: 99%

Integration and Packaging of a Macrochip With Silicon Nanophotonic Links

Cunningham

Krishnamoorthy

et al. 2011

IEEE J. Select. Topics Quantum Electron.

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“…Silicon photonics will eliminate the need for any off-chip wiring, such as between an SDRAM chip and a transceiver, improving the overall bandwidth, latency, and energy efficiency. By modulating and receiving the optical memory transactions within the memory and processor chips, we can achieve approximately 1 pJ/bit energy efficiency [18,19]. Continued development of silicon photonic technology is likely to improve this further.…”

Section: E Architectural Analysis and Discussionmentioning

confidence: 99%

“…Each optical link is also agnostic to bit rate, which can allow the transmission of terabits of data on a single fiber. Recent advances in silicon photonics have also enabled efficient coupling [17] for high-bandwidth density, as well as the fabrication of energy-efficient transceivers [18,19]. This work explores the architectural impact of optical interconnects enabling unprecedented growth and flexibility in large-scale computer systems.…”

Section: Optically Connected Memorymentioning

confidence: 99%

Building Data Centers With Optically Connected Memory

Brunina¹,

Lai

Garg

et al. 2011

J. Opt. Commun. Netw.

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Abstract-Future data centers will require novel, scalable memory architectures capable of sustaining high bandwidths while still achieving low memory access latencies. Electronic interconnects cannot meet the challenges presented by the need for multi-terabit off-chip memory data paths. In this work, the electronic bus between main memory and its host processor is replaced with a circuit-switched optical interconnection network. We investigate the impact of our optically connected memory system on large-scale architectures and experimentally validate the protocol using field-programmable gate array based processor nodes and a custom-designed memory controller. The processor communicates all-optically with multiple synchronous dynamic random access memory nodes using 4×2.5-Gb/s wavelength-striped payloads, operating error free with bit-error rates less than 10 −12 .

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“…However, significant progress has been made in providing such high-speed connections. Electrical bonding techniques for multi-chip integration include wire bonding [31], flip-chip bump bonding [32], (which provides reduced parasitic capacitance and higher density than wire bonding) and through-silicon vias [33], which offer even higher density and lower parasitics (see Figure 13). Copper pillar interconnects, at very low capacitance and high density, are already in production for electronics, and it is only a matter of time before they are used to attach high-performance CMOS and Bi-CMOS circuits to silicon photonic chips.…”

Section: Electronic-photonic Integrationmentioning

confidence: 99%

Progress in silicon platforms for integrated optics

Novack¹,

Streshinsky²,

Ding

et al. 2014

Nanophotonics

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Rapid progress has been made in recent years repurposing CMOS fabrication tools to build complex photonic circuits. As the field of silicon photonics becomes more mature, foundry processes will be an essential piece of the ecosystem for eliminating process risk and allowing the community to focus on adding value through clever design. Multi-project wafer runs are a useful tool to promote further development by providing inexpensive, low-risk prototyping opportunities to academic and commercial researchers. Compared to dedicated silicon manufacturing runs, multi-project-wafer runs offer cost reductions of 100 × or more. Through OpSIS, we have begun to offer validated device libraries that allow designers to focus on building systems rather than modifying device geometries. The EDA tools that will enable rapid design of such complex systems are under intense development. Progress is also being made in developing practical optical and electronic packaging solutions for the photonic chips, in ways that eliminate or sharply reduce development costs for the user community. This paper will provide a review of the recent developments in silicon photonic foundry offerings with a focus on OpSIS, a multiproject-wafer foundry service offering a silicon photonics platform, including a variety of passive components as well as high-speed modulators and photodetectors, through the Institute of Microelectronics in Singapore.

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Flip-chip integrated silicon photonic bridge chips for sub-picojoule per bit optical links

Cited by 27 publications

References 8 publications

Integration and Packaging of a Macrochip With Silicon Nanophotonic Links

Integration and Packaging of a Macrochip With Silicon Nanophotonic Links

Building Data Centers With Optically Connected Memory

Progress in silicon platforms for integrated optics

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