Flip chip on board connection technology: process characterization and reliability

Giesler, J.; O’Malley, Grace; Williams, Mike; Machuga, S.

doi:10.1109/96.311771

Cited by 38 publications

(20 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Moreover, Flip chip on board (FCOB) can provide the highest packaging density in 2D package [1]. Among various kinds of flip chip bumps, solder bump is the most important type for FCOB compared with stud and adhesive bumps [2].…”

Section: Introductionmentioning

confidence: 99%

Effect of reflow conditions on the die shear strength in flip chip on board with SAC305 solder joints

Zhou

Lin

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

View full text Add to dashboard Cite

Solder bump joint has been accepted as a main FCOB interconnection method so far. To optimize the process conditions for achieving SAC305 solder bumped FCOB assembly with maximum die shear strength and allowable void rate, an orthogonal experimental design of four factors and three levels was carried out. The optimal process conditions are: 100 seconds for preheating time, 245 o C for peak temperature, 60 seconds for time above liquidus, flux paste as the auxiliary material. Three fracture modes were observed and categorized for samples after shear test based on the fracture interface location. The most frequently occurring fracture mode is the ductile.

show abstract

Section: Introductionmentioning

confidence: 99%

Effect of reflow conditions on the die shear strength in flip chip on board with SAC305 solder joints

Zhou

Lin

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

View full text Add to dashboard Cite

show abstract

“…There are plenty of writings discussing the effect of underfill, which helps to mitigate the effects of large stresses induced by the mismatch of thermal expansion coefficient between organic / inorganic substrates and chips [1][2][3][4]. Moreover, underfill provides peripheral protection to the solder joints, delivering a practical solution to extend the application of flip-chip technology [5].…”

Section: Introductionmentioning

confidence: 99%

Achievement of low temperature chip stacking by a wafer-applied underfill material

Cheng

Kao

Chang

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

This paper will highlight recent developments of an efficient assembly technology for chip stacking which utilizes a novel wafer applied underfill (WAUF). The a-stage WAUF was spin coated on an 8" wafer with a bump structure of 5 um Cu / 3 um Ni / 5 um Sn2.5Ag Pb-free solder, and then baked at 125ºC for 40 minutes to form a 30 um thick b-stage film. After wafer dicing, four chips with WAUF were assembled via a SÜSS FC-150 bonder on a Si interposer. With the aid of the flux agent in the WAUF, the peak bonding temperature was lowered to 240ºC, which was beneficial for the reduction of residual thermal stress as compared to that imposed by direct bonding at 280ºC. Previous work showed that no delamination of WAUF was found in the chip stacking architecture after the precondition test. In the most recent study, a temperature cycling test (TCT, JESD22-A104-B, Condition B, Soak mode 2) was used to assess the reliability of the 20 um pitch microjoints sealed by the WAUF. After 250 TCT cycles, 87.5% test vehicles failed with a failure mode of the microjoints shown to be interfacial fracture. This was a similar result to the failure mode of microjoints sealed by capillary underfill, though the WAUF failed much earlier.The root-cause of the failure can be attributed to the inferior bonding accuracy, as the majority of the Sn2.5Ag solder alloy at the contact area completely reacted with Ni to form Ni 3 Sn 4 at this stage but did not link up with each other (a proposed failure mechanism will be given in another ITRI's paper). However, the lifespan of the microjoints could be prolonged if the remaining Sn2.5Ag Pb-free solder alloy is sufficient to sustain the bump structure after bonding, even though the WAUF was not post-cured. The authors believe that the newly developed underfill material and the corresponding assembly technology will reveal a proper technique for stacking homogeneous ICs (such as DRAM) efficiently and reliably.

show abstract

“…The shear strain in the solder connection during thermal cycling is reduced [9][10][11] at the cost of additional stress and strain in the other materials of the flip chip assembly. Delaminations between underfill and flip chip die passivation bear a high reliability risk for flip chip on board assemblies, since they result in an increase in the shear deformation in the solder [12,13] and act as nucleation sites for cracks in adjacent materials [14].…”

Section: Introductionmentioning

confidence: 99%

Rapid Interface Reliability Testing of Flip Chip Encapsulants

Rau¹,

Becker

Wunderle

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

View full text Add to dashboard Cite

A rapid interface reliability test for underfill materials in real flip chip on board assemblies consisting of autoclave aging at 121PC and 100% relative humidity, followed by vibrational stressing at room temperature has been developed. The moisture concentrations in the flip chip assembly have been calculated by Finite Element Simulations to determine an adequate autoclave aging period. An extended three parameter diffusion model based on Fick's law has been used. It considers an additional first order binding of the moisture and enables the modeling of a linear moisture absorption beyond the fickian saturation level, as observed for epoxies and polyimides. The diffusion properties and the adhesion of the underfiller are tested by the subsequent vibrational stressing. The results of linear-elastic finite element simulations show, that the vibrational test induces the same shear stresses and strains in the underfill material as those induced by the mismatch of the coefficient of thermal expansion (CTE) between board and chip in temperature cycling. However the CTE mismatch between underfill and its adjacent materials causes additional tensile stress and strain during temperature cycling, which are not induced by the vibrational test. Thus the rapid interface test is independent of the thermo-mechanical properties of the underfill material. It enables a fast selection of underfill materials with good adhesion in a humid environment, which suit applications in harsh environments. By using a defined test setup, in which only the underfill material is varied, the assessment period is reduced to less than a week. The advantage compared to standard material testing procedures is the use of a real flip chip assembly. Thus the materials are tested in the relevant dimensions and combinations processed in a manufacturing assembly flow.

show abstract

Flip chip on board connection technology: process characterization and reliability

Cited by 38 publications

References 2 publications

Effect of reflow conditions on the die shear strength in flip chip on board with SAC305 solder joints

Effect of reflow conditions on the die shear strength in flip chip on board with SAC305 solder joints

Achievement of low temperature chip stacking by a wafer-applied underfill material

Rapid Interface Reliability Testing of Flip Chip Encapsulants

Contact Info

Product

Resources

About