Flip-flop hardening for space applications

Monnier, Thierry; Roche, F.M.; Cathébras, Guy

doi:10.1109/mtdt.1998.705955

Cited by 15 publications

(9 citation statements)

References 10 publications

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“…In this case, additional hardening of combinational logic would not yield any improvement in the total sensitive cross-section due to the limit posed by the unhardened latches. Traditional hardening approaches such as DICE latches could be used to further improve the total sensitive cross-section [20].…”

Section: A Selective Hardening Of Sensitive Nodes By Transistor Sizingmentioning

confidence: 99%

Single-event mitigation in combinational logic using targeted data path hardening

Srinivasan

Sternberg

Duncan

et al. 2005

IEEE Trans. Nucl. Sci.

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Section: A Selective Hardening Of Sensitive Nodes By Transistor Sizingmentioning

confidence: 99%

Single-event mitigation in combinational logic using targeted data path hardening

Srinivasan

Sternberg

Duncan

et al. 2005

IEEE Trans. Nucl. Sci.

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“…A few harden CMOS inverters and cells have been presented in the past few years [9][10][11][12][13][14]. Some are limited by their lack of robustness to the longest upsets, others present prohibitive areas.…”

Section: The Seuhardened Hzlatchmentioning

confidence: 99%

Integration of Robustness in the Design of a Cell

Dutertre

Roche

Cathébras

2002

IFIP Advances in Information and Communication Technology

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Abstract:When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits undergo soft errors. Among these events the most worrying is an electrical upset, so called Single Event Upset (SEU) evidenced in latches. We present here the circuit architecture of a new SEU hardened latch. The hardening is based on an integrated redundancy of the information and a high impedance state switching. The design prevents perturbation to propagate inside the latch and saves an uncorrupted information source for recovery mechanisms. Post layout circuit simulations are used to verify the hardness assurance of this design; we also compare it to usual techniques and report significant improvements for its use in SoC.

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“…Although the TMR-latch is highly reliable and widely used, it suffers from high area and power consumption overheads which are not acceptable for applications where area and power consumption are the primary concerns. In contrast, some other techniques try to reduce these overheads by employing redundant components inside the latch [11][12][13][14][15]. In these techniques, some extra transistors are used to either suppress or recover from the SEU effect.…”

Section: Introductionmentioning

confidence: 99%

A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SETs

Fazeli

Miremadi

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (Single Event Transient and Upset Robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element to tolerate the effect of the SETs occurring in the input line of the latch as well as SEUs occurring inside the latch. The experimental results show that the probability of an SET resulting in a soft error can be reduced up to 90% by choosing a proper delay value. The soft error rate of the SETUR due to SEUs occurring inside the latch is reduced by 95% while having lower area, power and performance overhead than the previously proposed latches.

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Flip-flop hardening for space applications

Abstract: The purpose of this work is to design a Flip-flop hardened to Single Event Upset (SEU) for space radiation environment. The design hardening technique is based on the use of two Dlatch hardened both to static and dynamic SEU by the concepts of high impedance state and nMOS feedback.

Cited by 15 publications

References 10 publications

Single-event mitigation in combinational logic using targeted data path hardening

Single-event mitigation in combinational logic using targeted data path hardening

Integration of Robustness in the Design of a Cell

A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SETs

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