The purpose of this work is to design a Flip-flop hardened to Single Event Upset (SEU) for space radiation environment. The design hardening technique is based on the use of two Dlatch hardened both to static and dynamic SEU by the concepts of high impedance state and nMOS feedback.

International audienceA novel memory structure, designed to tolerate SEU perturbations, has been implemented in registers and tested. The design was completed using a standard submicron non-radiation hardened CMOS technology. This paper presents the results of heavy ion tests which evidence the noticeable improvement of the SEU-robustness with an increased LET threshold and reduced cross-section, without significant impact on the real estate, write time, or power consumption

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