SEU testing of a novel hardened register implemented using standard CMOS technology

Monnier, Thierry; Roche, F.M.; Cosculluela, J.; Velazco, Raoul

doi:10.1109/23.819105

Cited by 16 publications

(7 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For instance, this approach is adopted by the latches in [19,20,21,18,22,23]. In particular, the robustness of [19,20,21,18] derives from the idea of either splitting the internal nodes and adopting proper feedback structures, or using a Schmitt trigger-like scheme.…”

Section: Introductionmentioning

confidence: 99%

“…In particular, the robustness of [19,20,21,18] derives from the idea of either splitting the internal nodes and adopting proper feedback structures, or using a Schmitt trigger-like scheme. Instead, solutions in [22,23] improve the latch robustness by inserting either explicit capacitances, or transistors acting as filters for voltage glitches. All latches in [19,20,21,18,22,23] include nodes that, if affected by a TFs, may produce an output SE.…”

Section: Introductionmentioning

confidence: 99%

“…Instead, solutions in [22,23] improve the latch robustness by inserting either explicit capacitances, or transistors acting as filters for voltage glitches. All latches in [19,20,21,18,22,23] include nodes that, if affected by a TFs, may produce an output SE.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Performance Robust Latches

Omaña

Rossi

Metra

2010

IEEE Trans. Comput.

View full text Add to dashboard Cite

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/). Abstract-First a new high performance robust latch (referred to as HiPeR latch) is presented, that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed, that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good tradeoffs in terms of performance, robustness and cost, our proposed latches are particularly suitable to be adopted on critical paths.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High-Performance Robust Latches

Omaña

Rossi

Metra

2010

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…The first approach of hardened latch filters out the transition faults from entering into internal nodes. Previous designs focused on adding capacitance [53] and for filter, adding RC filters [54] resulting in more area and power consumption. Duplicating the nodes within the latch is considered as first hardening approach for filter the TFs which cause Soft Errors.…”

Section: Cmos Srammentioning

confidence: 99%

Single Event Upset Detection and Hardening schemes for CNTFET SRAM – A Review

Rajalakshmi¹,

Sudhakar²

2015

JESTR

View full text Add to dashboard Cite

Carbon nanotubes (CNT) provide a better alternative of silicon, when it comes to nano scales. Thanks to its high stability and high performance of carbon nanotube, CNT based FET (CNTFET) devices which are gaining popularity of late. Single Event Upset (SEU) in a device is caused due to radiation. Radiation can be through two ways, one due to charge particles present in the atmosphere and other due to alpha particles. In this article we review some of the detection and hardening schemes in CMOS SRAM and make related simulations on CNTFET SRAM. The aim of this paper is to present the challenges the CNTFET SRAM is facing when the radiation effects are introduced. A full experimentation of all the schemes of detection and correction schemes will be beyond the scope, so only certain experiments that can be well carried out with CNTFET SRAM memory is more focussed.

show abstract

“…The test vehicle consists of twelve independent shift registers. Each of them combine a set of 40 D-latches organized into 20 flip-flops [16]. Half of the registers are designed with CMOS standard cell D-latches ( Fig.1), the other half with rad tolerant ones (Fig.2).…”

Section: A Device Descriptionmentioning

confidence: 99%

Improving an SEU hard design using a pulsed laser

Dutertre

Roche

Fouillat³

et al.

RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605)

Self Cite

View full text Add to dashboard Cite

The purpose of this work is to present one investigation utilizing a pulsed laser as a tool to improve the Single Event Upset tolerance of a memory cell. These results coming with a previous ion testing evaluation of the circuit allow an optimization of the design. The laser results permit a more detailed analysis of the phenomenon leading to the upset and a precise localization of the most sensitive areas. As a result the behavior verification of the design combined with the use of robust elementary blocks strengthens the hardening capabilities of the cell.

show abstract

SEU testing of a novel hardened register implemented using standard CMOS technology

Cited by 16 publications

References 12 publications

High-Performance Robust Latches

High-Performance Robust Latches

Single Event Upset Detection and Hardening schemes for CNTFET SRAM – A Review

Improving an SEU hard design using a pulsed laser

Contact Info

Product

Resources

About