Floating-Gate energy recovery logic

Cisneros-Sinencio, Luis F.; Díaz-Sánchez, A.; Ramírez-Angulo, J.; Graciós-Marin, C.A.

doi:10.1109/mwscas.2009.5236040

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…The macro model of the FGMOS transistor [1,27] given in Fig. A2 is used to simulate it to overcome the issue of dc con-…”

Section: Appendix a Floating Gate Mosfetmentioning

confidence: 99%

“…Current mode active building blocks offer a wide dynamic range, good linearity and higher bandwidth with low supply voltage over their voltage mode counterparts. Various low voltage analog techniques including bulk driven, selfcascode, sub-threshold MOSFETs, and floating gate MOS-FETs [1][2][3] exist in the literature to design low voltage current mode based systems while meeting design specifications. FGMOSFET is the most suitable technique for low voltage low power analog applications as it reduces or removes the dependency on threshold voltage.…”

Section: Introductionmentioning

confidence: 99%

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Low voltage floating gate MOSFET based current differencing transconductance amplifier and its applications

Rana¹,

Prasad²,

Afzal³

2018

J. Semicond.

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This article presents a low voltage low power configuration of current differencing transconductance amplifier (CDTA) based on floating gate MOSFET. The proposed CDTA variant operates at lower supply voltage ±1.4 V with total static power dissipation of 2.60 mW due to the low voltage feature of floating gate MOSFET. High transconductance up to 6.21 mA/V is achieved with extended linear range of the circuit i.e. ±130 μA. Two applications are illustrated to demonstrate the effectiveness of the proposed active block. A quadrature oscillator is realized using FGMOS based CDTA, two capacitors, and a resistor. The resistor is implemented using two NMOSFETs to provide high linearity and tunablility. Another application is the Schmitt trigger circuit based on the proposed CDTA variant. All circuits are simulated by using SPICE and TSMC 130 nm technology.

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“…The macro model of the FGMOS transistor [1,27] given in Fig. A2 is used to simulate it to overcome the issue of dc con-…”

Section: Appendix a Floating Gate Mosfetmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%