Fluorine effect on boron diffusion of p/sup +/ gate devices (MOSFETs)

Sung, J.M.; Lu, Chih‐Yuan; Chen, M.L.; Hillenius, S.J.; Lindenberger, W.S.; Manchanda, L.; Smith, T. E.; Wang, S.J.

doi:10.1109/iedm.1989.74318

Cited by 23 publications

(9 citation statements)

References 9 publications

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“…In particular, the absence of a threshold voltage shift in the p-MOSFET characteristics guarantees the nonexistence of disrupting B penetration from the gate electrodes, which would have been thought to be a primary concern for high-dose F implantation into B-doped poly-Si gate electrodes. 19) In addition, the lack of influence on the short-channel effect also indicates the unperturbed nature of the junction profiles by F-PSII. Figure 16 demonstrates the on-current I on vs off-current I off characteristics of (a): n-MOSFET and (b): p-MOSFET with F-PSII (closed circles) and without F-PSII (open circles).…”

Section: Cmos Fabrication With F-psiimentioning

confidence: 99%

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

Tsuchiaki

Ohuchi

Nishiyama

2005

Jpn. J. Appl. Phys.

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To date, various connection rerouting methods for connection-oriented mobile networks have been proposed. The previous methods, however, are limited to specific topologies or environments. In this paper, we propose the connection-information-based rerouting widely applicable to various connection-oriented mobile networks. This method requires neither a specific topology nor a complex connection, enables fast rerouting, provides appropriate route optimality, and can be extended easily.

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Section: Cmos Fabrication With F-psiimentioning

confidence: 99%

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

Tsuchiaki

Ohuchi

Nishiyama

2005

Jpn. J. Appl. Phys.

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“…Boron penetration into the oxide or the channel is therefore a major concern for deep sub-micron CMOS technology [1,2] particularly with the thermal budgets and ultra-thin gate dielectrics required in today's CMOS processes. The addition of fluorine, introduced by implantation with BF 2 , or exposure to hydrogen containing ambients is shown to accelerate the rate of boron diffusion through thin gate dielectrics [3,4,5]. Dielectric thickness scaling is also demonstrated to result in a rapid increase in the level of boron penetration for a given set of thermal process conditions.…”

Section: Introductionmentioning

confidence: 98%

Nitric Oxide Rapid Thermal Nitridation of Thin Gate Oxides

et al. 1997

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Nitric oxide rapid thermal nitridation of thin gate oxides was investigated. Oxides from 25 to 55 A were grown in 02 and subsequently nitrided in a nitric oxide (NO) ambient using an Applied Materials RTP Centura chamber. Nitrogen incorporation and film thickness growth during NO nitridation were evaluated. Peak nitrogen incorporation was most strongly influenced by temperature and time, with moderate influence by initial oxide thickness, and no significant influence due to NO flow rate. Peak nitrogen concentrations ranged from 1 to 9 atomic percent as characterized by Secondary Ion Mass Spectrometry (SIMS) analysis. Oxide growth during nitridation ranged from 2 A to II A with no degradation in uniformity. These data were used in the design of two 40 A oxynitride processes incorporating 2 and 4 peak atomic percent nitrogen. High quality MOS capacitors were demonstrated with these dielectrics. Performance was compared against a baseline furnace process as well as non-nitrided RTO. Throughout this work, the chamber integrity was monitored using visual inspection, minority carrier lifetime (MCLT) and surface photovoltage (SPV). No contamination, corrosion or other degradation of the process chamber was observed in over 6 months' operation with over 700 NO processes completed. The controllability, uniformity and high nitrogen incorporation of rapid thermal NO nitridation make it an attractive process for deep sub-micron gate insulators.

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“…Fluorine is usually introduced through the use of the BF implant species to obtain shallow junction formation for the PMOS devices, to reduce shortchannel effects. Boron penetration has been shown to cause enhanced threshold voltage variation [2], [5].…”

Section: Introductionmentioning

confidence: 99%

Improvement in threshold voltage control by minimizing boron penetration in a LV-GCMOS technology

John

Teplik²,

Hildreth³

et al. 1998

IEEE Trans. Semicond. Manufact.

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Maintaining tight threshold voltage (V T V T V T ) control for a low-voltage CMOS process is critical due to the large impact of V T V T V T on circuit performance at low power supply voltages. In this paper, PMOS V T V T V T was shown to be sensitive to poly gate thickness and BF + + + 2 source/drain implant energy. This data helped identify boron penetration as a prime contributor to PMOS threshold voltage variation. SIMS measurements were used to investigate boron diffusion through the poly gate at various stages in the process flow. These SIMS profiles pointed to the low-temperature thermal cycle of the nitride spacer deposition as a key step which influenced the amount of boron penetration and thus the final device threshold voltage. Experimental evidence shows that the temperature gradient across the nitride spacer deposition furnace causes a variable amount of boron penetration resulting in a large variation in PMOS VT VT VT . We adopted a process flow change which virtually eliminated boron penetration and significantly reduced the sensitivity of the devices to manufacturing variations. Threshold voltage variation was reduced by a factor of two.

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Fluorine effect on boron diffusion of p/sup +/ gate devices (MOSFETs)

Cited by 23 publications

References 9 publications

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

Nitric Oxide Rapid Thermal Nitridation of Thin Gate Oxides

Improvement in threshold voltage control by minimizing boron penetration in a LV-GCMOS technology

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