Formal design procedures for pass transistor switching circuits

Radhakrishnan, D.; Whitaker, S.; Maki, G.K.

doi:10.1109/jssc.1985.1052339

Cited by 88 publications

(26 citation statements)

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“…While there have been several attempts in this area ( [3] [7][10] [13][15] [16][17] [18] [22]), limitations of some of which are discussed later in the paper, there are no algorithms which can be used to design safe, large PTL circuits. Thus, while designers can manually design very efficient small PTL circuits as in Fig.…”

Section: Introductionmentioning

confidence: 99%

Logic synthesis for large pass transistor circuits

Buch

Narayan

Newton

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

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Section: Introductionmentioning

confidence: 99%

Logic synthesis for large pass transistor circuits

Buch

Narayan

Newton

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

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“…PMOS and NMOS are in parallel and are controlled by complementary signals. Both transistors are ON or OFF simultaneously [8]. The NMOS switch passes a good zero but a poor 1.…”

Section: Transmission Gate Logicmentioning

confidence: 99%

A Comparative Performance Analysis of Various CMOS Design Techniques for XOR and XNOR Circuits

Joshi¹

2017

IJRASET

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“…The low power pass-transistor logic and its design analysis procedures were reported in [12,13]. Its advantage is that one passtransistor network (either pMOS or nMOS) is sufficient to implement the logic function, which results in lower number of transistors and smaller input load.…”

Section: Review Of Full Adder Topologiesmentioning

confidence: 99%

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

2012

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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

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Formal design procedures for pass transistor switching circuits

Cited by 88 publications

References 0 publications

Logic synthesis for large pass transistor circuits

Logic synthesis for large pass transistor circuits

A Comparative Performance Analysis of Various CMOS Design Techniques for XOR and XNOR Circuits

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

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