Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths

Chen, Liang; Ebrahimi, Mojtaba; Tahoori, Mehdi B.

doi:10.1007/s10836-015-5519-3

Cited by 17 publications

(7 citation statements)

References 43 publications

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“…In recent years, several techniques, such as fault simulation 24,25 and formal verification, 26,27 have been proposed to evaluate the reliability of logic circuits at RTL. The basic idea of the simulation-based techniques is to produce or simulate faults during system operation and compare the output logics of the circuit with and without faults to evaluate its reliability.…”

Section: Reliability Analysismentioning

confidence: 99%

“…However, reduction techniques are often used to handle circuits with moderate or large sizes to meet their fast computing requirement, which tends to result in accuracy loss. For example, Chen et al 26 modeled the behaviors of RTL circuits as finite discrete‐time Markov chains, but partitioning techniques and data‐type reduction are required to overcome the state explosion problem. Shazli and Tahoori 27 transformed the reliability problem into an equivalent Boolean satisfiability (SAT) problem and used SAT‐solvers to obtain the soft error rate of the given circuits.…”

Section: Related Workmentioning

confidence: 99%

“…However, the model has high complexity when dealing with basic RTL arithmetic operations 22 . By Kazma et al, 22 an approach was proposed to model the propagation of the faults as an SAT problem using satisfiability modulo theories to estimate the vulnerability of combinational circuits to soft errors, in which the data‐type reduction technique presented by Chen et al 26 was applied to reduce the difficulty of the problem being analyzed.…”

Section: Related Workmentioning

confidence: 99%

“…However, they are not conducive to measuring the reliability of the functional blocks that make up the circuits, 22,23 which makes them unfavorable for the implementation of selective hardening operations based on functional blocks. Therefore, the propagation of soft errors in logic circuits was analyzed at register transfer level (RTL) by various researchers using fault simulation 24,25 and formal verification methods 26,27 . However, the methods have difficulty balancing the evaluation accuracy and calculation overhead effectively.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing

Xiao

Shen

et al. 2022

Int J of Intelligent Sys

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Reliable circuits help prevent artificial intelligence (AI) systems from being corrupted by the soft errors occurred in memories or combinational circuits, which promotes the development of AI security. However, it is a great challenge to measure the reliability of combinational circuits at register transfer level (RTL) rapidly and efficiently. In this paper, a new fast and accurate computational model based on stochastic computation (SC) is presented to meet these objectives.In the proposed approach, the circuit netlists at RTL are parsed to satisfy the requirements of SC on the bitstream structure of the circuits, and then a Sobol sequence-based algorithm for generating uniform non-Bernoulli sequences is built to reduce the random fluctuations occurred in probability calculations. After that, an adaptive algorithm based on a MAX-MIN ant system is constructed using graphics processing unit-based parallel schemes to greatly accelerate the calculation. The experimental results validate our proposed technique, showing that this approach was approximately 51 and 42 times faster than the traditional SC approach and the stochastic computational model (SCM), respectively; its required sequence length was approximately 1.66 times shorter than that

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Section: Reliability Analysismentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing

Xiao

Shen

et al. 2022

Int J of Intelligent Sys

View full text Add to dashboard Cite

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“…A comprehensive analysis of sequential and combinational soft errors for the embedded processors is proposed in [19]. In [20], a quantification method for register vulnerabilities to soft error in register transfer logic (RTL) is proposed.…”

Section: Related Workmentioning

confidence: 99%

Design of a Radiation Hardened Register File for Highly Reliable Microprocessors

Rajaei

2016

IJEM

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In this paper, a powerful bit upset masking (PBUM) technique for design of a high reliable register file is proposed. This technique is based on the triple modular redundancy (TMR) technique with the key capability of double faulty bit masking in every triad of bits while the TMR structure, only masks one fault in a triad. We implemented a 64-bit register file comprised of 64 registers protected with the proposed PBUM technique on FPGA. Our simulation results reveal that, over the TMR and some Hamming code-based techniques, our design offers a very higher robustness against radiation induced soft errors. Also, the proposed PBUM technique imposes a lower delay than its counterparts at the expense of a little higher area overhead. To reduce the area overhead, an area-efficient strategy is suggested that balances the reliability improvement and the area overhead. We show that, our technique using this area-aware strategy still has the highest reliability among the other considered techniques.

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State ordering and classification for analyzing non-sparse large Markov models

Mohagheghi

2024

J Supercomput

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Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths

Cited by 17 publications

References 43 publications

Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing

Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing

Design of a Radiation Hardened Register File for Highly Reliable Microprocessors

State ordering and classification for analyzing non-sparse large Markov models

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