Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test

Eggersglüβ, Stephan; Holst, Stefan; Tille, Daniel; Miyase, Kohei; Wen, Xiaoqing

doi:10.1109/ats.2016.41

Cited by 12 publications

(2 citation statements)

References 25 publications

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“…Tables 3 to 5 present these categories. Launch-off capture (LOC) usage † [12], [17], [18], [20], [22]- [27], [28]- [31], [33] 3…”

Section: Classificationmentioning

confidence: 99%

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A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

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“…Tables 3 to 5 present these categories. Launch-off capture (LOC) usage † [12], [17], [18], [20], [22]- [27], [28]- [31], [33] 3…”

Section: Classificationmentioning

confidence: 99%

“…A technique to reduce at-speed scan capture power by adding test points is presented in [17]. Lowcapture-power test points (LCP-TPs) are used to reduce LSA in high-capture-power (HCP) regions while maintaining fault coverage and a low test-pattern count.…”

Section: Test Point Insertionmentioning

confidence: 99%