Formation of atomic-scale germanium quantum dots by selective oxidation of SiGe/Si-on-insulator

Abstract

SiGe-on-insulator substrate fabricated by melt solidification for a strained-silicon complementary metal-oxide-semiconductor J.

Designer Ge quantum dots on Si: A heterostructure configuration with enhanced optoelectronic performance

“…[18][19][20][21] During SiGe oxidation, the Si content is preferentially oxidized, releasing Ge to be incorporated within the as-yet unoxidized SiGe regions. Thus, Ge QDs are ultimately formed by a progressive "concentration" of the Ge content within the remaining unoxidized portions of SiGe grains until the entire Si is used up, ultimately leaving Ge QDs embedded within the newly formed SiO 2 layer.…”

Controlled Heterogeneous Nucleation and Growth of Germanium Quantum Dots on Nanopatterned Silicon Dioxide and Silicon Nitride Substrates

“…Ge QDs have been fabricated on oxide, nitride, or oxynitride substrates. We have successfully demonstrated several capabilities, including the ability to grow dense arrays of Ge QDs by thermal oxidation of planar SiGe-on-insulator layers, , as well as the precise placement and size control of Ge QDs within nanopatterned structures being reported in this paper. We believe that this new capability of precise placement and size control of Ge QDs on SiO 2 and Si 3 N 4 substrates offers exciting possibilities for generating new classes of quantum tunneling devices, such as single-electron devices, single-photon light sources (SPSs), and possibly charge quantum bit devices.…”

Electrical characteristics of MIS capacitors with multi-stack thermal-agglomerating Ge nanocrystals in SiO2/SiNx dielectrics

“…Si NCs/silicon nitride (SiN) and Au NCs/SiN heterogeneous stacks in metal-nitride-oxide-silicon (MNOS) structure have been proposed by Yamazaki et al [10] and Lee et al [11], respectively. Besides, it has been reported that Ge would diffuse into Si substrate during thermal oxidation of SiGe films and thermal-annealing of oxide/Ge/oxide multilayers [8,12]. Ng et al reported the use of SiN/HfO 2 stack as a tunnel dielectric to suppress the Ge penetration during subsequent annealing process to form Ge NCs [12].…”

“…Memory devices employing Ge NCs instead of Si NCs would have better performance [5]. Various techniques, such as ion implantation into SiO 2 [6], co-sputtering of Ge and SiO 2 [7] and oxidation of SiGe layer [8], had been employed to fabricate Ge NCs in SiO 2 matrix.…”