Formation of Ultra-thin and Uniform Ni-InGaAs Alloyed Contact for Scaled Metal S/D InGaAs MOSFETs

Abstract

Thickness controllability and thermal stability of Ni-InGaAs alloyed contact have been investigated with the aim of the applications to scaled metal S/D InGaAs MOSFETs. Low sheet resistance (~25 /□) Ni-InGaAs alloyed layers with the thickness as thin as 6 nm, which meets the requirement of scaled metal S/D MOSFETs (Lg < ~50 nm), have been formed by reducing evaporated Ni thickness and annealing temperature. It was found that the ultra-thin and smooth alloyed layer maintained after additional annealing at temperatures up to 250˚C. These results suggest that low temperature BEOL processes (< 250˚C) would enable us to utilize Ni-InGaAs alloyed contacts in scaled metal S/D devices.

Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

“…6). Thermal stability up to at least 400 • C was obtained, which is quite high compared with the typical thermal stability of Ni-InGaAs (300 • C) [18], [19]. Here, it should be noted that the Ni composition of Ni-InGaAs formed with thin initial Ni thickness is higher than that of Ni-InGaAs formed with relatively thick initial Ni thickness.…”

“…A possible reason for roughened surface would be related to the phase change and lattice constant change with annealing temperature [43]. Sequential annealing at high temperature after first annealing at low temperature may be helpful to alleviate morphology issue as one can see from silicide and Ni-InP technologies [17], but it seems to be not so effective for Ni-InGaAs system [18].…”

In0.53Ga0.47As N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Shallow Metallic Source and Drain Extensions and Offset N+ Doped Regions for Leakage Suppression

“…Ni-InGaAs agglomerates and gives poor junction abruptness on InGaAs after being annealed at high temperatures. 40) Schematics of key process steps are illustrated in Fig. 2.…”