Foundations of memristor based PUF architectures

Rose, Garrett S.; McDonald, Nathan; Yan, Lok-Kwong; Wysocki, Bryant; Xu, Karen

doi:10.1109/nanoarch.2013.6623044

Cited by 60 publications

(51 citation statements)

References 23 publications

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“…The source of random information varies widely among proposed PUF architectures, and includes transistor threshold voltages [4], delay chains and ring oscillators (RO) [2][3][4][5][6], FPGAs [7,8], SRAMs [9], leakage current [10], metal resistance [11], transistor transconductance [12], the path delays of core logic macros [13][14][15], memristors [16], scan chains [17], phase change memory [18], plus many others.…”

Section: Related Workmentioning

confidence: 99%

Analysis of Entropy in a Hardware-Embedded Delay PUF

et al. 2017

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Abstract:The magnitude of the information content associated with a particular implementation of a Physical Unclonable Function (PUF) is critically important for security and trust in emerging Internet of Things (IoT) applications. Authentication, in particular, requires the PUF to produce a very large number of challenge-response-pairs (CRPs) and, of even greater importance, requires the PUF to be resistant to adversarial attacks that attempt to model and clone the PUF (model-building attacks). Entropy is critically important to the model-building resistance of the PUF. A variety of metrics have been proposed for reporting Entropy, each measuring the randomness of information embedded within PUF-generated bitstrings. In this paper, we report the Entropy, MinEntropy, conditional MinEntropy, Interchip hamming distance and National Institute of Standards and Technology (NIST) statistical test results using bitstrings generated by a Hardware-Embedded Delay PUF called HELP. The bitstrings are generated from data collected in hardware experiments on 500 copies of HELP implemented on a set of Xilinx Zynq 7020 SoC Field Programmable Gate Arrays (FPGAs) subjected to industrial-level temperature and voltage conditions. Special test cases are constructed which purposely create worst case correlations for bitstring generation. Our results show that the processes proposed within HELP to generate bitstrings add significantly to their Entropy, and show that classical re-use of PUF components, e.g., path delays, does not result in large Entropy losses commonly reported for other PUF architectures.

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Section: Related Workmentioning

confidence: 99%

Analysis of Entropy in a Hardware-Embedded Delay PUF

et al. 2017

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“…Leveraging the intrinsic controlled sensitivity to processvariation effects, memristor-based circuits (usually in a hybrid form combined with CMOS) has been proposed to operate as hardware security primitives, particularly as PUF circuits [7,[20][21][22][23][24]]. The combination is made possible by the fact that the memristor manufacturing technology is compatible with modern CMOS fabrication standards [22], which provides memristors a distinct advantage compared to many other nano-devices.…”

Section: Memristor Based Hardware Security Primitivesmentioning

confidence: 99%

“…The combination is made possible by the fact that the memristor manufacturing technology is compatible with modern CMOS fabrication standards [22], which provides memristors a distinct advantage compared to many other nano-devices. Memristor-based PUFs have the advantages of lower area compared to CMOS-only hardware security primitives.…”

Section: Memristor Based Hardware Security Primitivesmentioning

confidence: 99%

“…There are two main ideas behind using memristors as PUF circuits, and the protocols built around them: write-time based output response variation [20][21][22] and variation of output voltages in memristor-based crossbar "polynominoes" [7,23,24]. We describe these two schemes in detail below.…”

Section: Memristor Based Hardware Security Primitivesmentioning

confidence: 99%

“…However, if "weak write" is performed on the device, with the chosen actual write-time t wr;actual very close in value to t wr;min , then because of process-variation effects of D, the output of the device becomes unpredictable. This effect is utilized to build a memristor-based PUF [20,22], where after a weak write operation, the memristor value is read (using CMOS digital gate in [22] and sense amplifier in [25]) to get the response. One of the interesting features of the architecture of the PUF proposed in [20] is that 1-bit of challenge results in 1-bit of response, while the architecture of [22] is more traditional where the challenge is used as an address to read a 1-bit value from a memory array.…”

Section: Write-time Based Memristor Pufmentioning

confidence: 99%

See 2 more Smart Citations

A novel memristor based physically unclonable function

Mathew

Chakraborty

Sahoo

et al. 2015

Integration, the VLSI Journal

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Machine Learning Attacks‐Resistant Security by Mixed‐Assembled Layers‐Inserted Graphene Physically Unclonable Function

Lee,

Jang,

Kim

et al. 2023

Advanced Science

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Mixed layers of octadecyltrichlorosilane (ODTS) and 1H,1H,2H,2H‐perfluorooctyltriethoxysilane (FOTS) on an active layer of graphene are used to induce a disordered doping state and form a robust defense system against machine‐learning attacks (ML attacks). The resulting security key is formed from a 12 × 12 array of currents produced at a low voltage of 100 mV. The uniformity and inter‐Hamming distance (HD) of the security key are 50.0 ± 12.3% and 45.5 ± 16.7%, respectively, indicating higher security performance than other graphene‐based security keys. Raman spectroscopy confirmed the uniqueness of the 10,000 points, with the degree of shift of the G peak distinguishing the number of carriers. The resulting defense system has a 10.33% ML attack accuracy, while a FOTS‐inserted graphene device is easily predictable with a 44.81% ML attack accuracy.

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Foundations of memristor based PUF architectures

Cited by 60 publications

References 23 publications

Analysis of Entropy in a Hardware-Embedded Delay PUF

Analysis of Entropy in a Hardware-Embedded Delay PUF

A novel memristor based physically unclonable function

Machine Learning Attacks‐Resistant Security by Mixed‐Assembled Layers‐Inserted Graphene Physically Unclonable Function

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