FPGA-Based Anomalous Trajectory Detection Using SOFM

Appiah, Kofi; Hunter, Andrew; Kluge, Tino; Aiken, Philip; Dickinson, Patrick

doi:10.1007/978-3-642-00641-8_24

Cited by 6 publications

(4 citation statements)

References 24 publications

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“…The system in [6] uses several digital signal processors on different PCI-boards, while the CITRIC [7] relies on the Intel XScale PXA270 processor. FP-GAs are used in systems such as [5] mostly as co-processor just for accelerating a single function. In [5] a Xilinx Spartan-3E FPGA is used as a co-processor.…”

Section: Related Workmentioning

confidence: 99%

“…FP-GAs are used in systems such as [5] mostly as co-processor just for accelerating a single function. In [5] a Xilinx Spartan-3E FPGA is used as a co-processor. In [17], a hardware/software implementation on a Xilinx FPGA platform is presented for a 3D facial pose tracking application; the most-computationally intensive part is implemented in hardware while the remaining is implemented in the soft-core processors.…”

Section: Related Workmentioning

confidence: 99%

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A framework for rapid prototyping of embedded vision applications

Mefenza

Yonga

Saldanha

et al. 2014

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

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We present a framework for fast prototyping of embedded video applications. Starting with a high-level executable specification written in OpenCV, we apply semi-automatic refinements of the specification at various levels (TLM and RTL), the lowest of which is a system-on-chip prototype in FPGA. The refinement leverages the structure of image processing applications to map high-level representations to lower level implementation with limited user intervention. Our framework integrates the computer vision library OpenCV for software, SystemC/TLM for high-level hardware representation, UVM and QEMU-OS for virtual prototyping and verification into a single and uniform design and verification flow. With applications in the field of driving assistance and object recognition, we prove the usability of our framework in producing performance and correct design.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A framework for rapid prototyping of embedded vision applications

Mefenza

Yonga

Saldanha

et al. 2014

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

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show abstract

“…Reliability and security of reconfigurable systems must be ensured within a multiparty environment, and in critical applications, for example, aerospace and defence , telecoms [Hutchings et al 2002;Salefski and Caglar 2001], and surveillance [Appiah et al 2009;Mühlbauer and Bobda 2006;Ngo et al 2005].…”

Section: Introductionmentioning

confidence: 99%

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems

Kȩpa

Morgan

Kosciuszkiewicz

et al. 2010

ACM Trans. Reconfigurable Technol. Syst.

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The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP core design assurance, particularly in multiparty Partially Reconfigurable (PR) designs. While tools for low-level analysis of design netlists do exist, there is increasing demand for automated and customisable bitstream analysis tools.This article discusses the need for low-level IP core verification within PR-enabled FPGA systems and reports FDAT (FPGA Design Analysis Tool), a versatile, modular and open tools framework for low-level analysis and verification of FPGA designs. FDAT provides a set of high-level Application Programming Interfaces (APIs) abstracting the Xilinx FPGA fabric, the implemented design (e.g., placed and routed netlist) and the related bitstream. A lightweight graphic frontend allows custom visualisation of the design within the FPGA fabric. The operation of FDAT is governed by "recipe" scripts which support rapid prototyping of the abstract algorithms for system-level design verification. FDAT recipes, being Python scripts, can be ported to embedded FPGA systems, for example, the previously reported Secure Reconfiguration Controller (SeReCon) which enforces an IP core spatial isolation policy in order to provide run-time protection to the PR system.The paper illustrates the application of FDAT for bit-pattern analysis of Virtex-II Pro and Virtex-5 inter-tile routing and verification of the spatial isolation between designs.

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“…Among them, concerning the studies for classifiers, e.g., [1]- [4] uses the technics of artificial neural networks. Another studies, e.g., [5]- [8] uses the other technics such as the AdaBoost algorithm, the wavelet transform and the nearest neighbor.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-based fast classifier with high generalization property

Horita

Takanami²

2010

SIGARCH Comput. Archit. News

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This paper proposes a scheme to implement classifiers with high generalization properties on FPGAs. The classifiers consist of only combinational logic circuits, which are based on a simple concept, and the VHDL source files which describe the classifiers are generated by a C-language function, tuning VHDL notations for adders in them to reduce both its hardware size and computation time. Simulation results based on a character recognition are shown in terms of generalization property, hardware size, computation time, and electricity consumption.

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FPGA-Based Anomalous Trajectory Detection Using SOFM

Cited by 6 publications

References 24 publications

A framework for rapid prototyping of embedded vision applications

A framework for rapid prototyping of embedded vision applications

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems

An FPGA-based fast classifier with high generalization property

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