FPGA-Based Circuit Model Emulation of Quantum Algorithms

Aminian, Mehdi; Saeedi, Mehdi; Zamani, Morteza Saheb; Sedighi, Mehdi

doi:10.1109/isvlsi.2008.43

Cited by 36 publications

(22 citation statements)

References 10 publications

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“…The presented VHDL model is unique from previous VHDL work [31,35,42] in that the resulting module may receive commands to implement an arbitrary operation on an arbitrary qubit at runtime, whereas the other work involved a hard-coded circuit pre-defined at compilation time.…”

Section: Discussionmentioning

confidence: 99%

“…Udrescu presented simulation models of quantum circuits using VHDL [30][31][32]. Negovetic et al [33] and Khalid [34] went even further to simulate quantum circuits using FPGA, and Aminian et al [35] worked on enhancing that. It is to note here that VHDL or FPGA can only be used to simulate quantum circuits, but cannot be used to produce quantum circuits by synthesis, since VHDL and FPGA are originally designed to target classical digital circuits rather than quantum circuits.…”

Section: Related Workmentioning

confidence: 99%

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Model of a hybrid processor executing C++ with additional quantum functions

Elhoushi

El-Kharashi

Elrefaei

2014

Microprocessors and Microsystems

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Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Model of a hybrid processor executing C++ with additional quantum functions

Elhoushi

El-Kharashi

Elrefaei

2014

Microprocessors and Microsystems

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“…For this purpose, simulation of quantum computers is highly demanded. Simulation of quantum computers is a time consuming task, and many simulation methods have been investigated intensively [1]- [16]. Some of them implement the simulator on an LSI [1], [5], [8], [11].…”

Section: Introductionmentioning

confidence: 99%

“…Indeed, in their experiments, the number of quantum bits of the target quantum circuits is 3. In [1], it is shown that by adding several quantum circuit primitives to those in [8], a lot of quantum algorithms can be simulated quickly and the size of the emulator circuit can be decreased. However, the number of quantum bits and quantum gates that can be simulated are still limited.…”

Section: Introductionmentioning

confidence: 99%

“…The size of logic circuits of the proposed architecture does not depend on the size of the quantum circuit to be simulated. * * * * * Thus, the proposed architecture is scalable in contrast to the hardware quantum circuit simulators in [1], [8], [11]. Also, the proposed architecture does not use complex inter-connection networks, but uses register reordering in order to select necessary register values.…”

Section: Introductionmentioning

confidence: 99%

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A Fast Quantum Computer Simulator Based on Register Reordering

Nakanishi

Matsuyama

Yokoo

2016

IEICE Trans. Inf. & Syst.

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SUMMARY Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on hardware that can process a lot of operations in parallel. In this paper, we propose a hardware quantum computer simulator. The proposed simulator is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implement the simulator on an FPGA. Experiments show that the proposed simulator has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.

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Scaling reconfigurable emulation of quantum algorithms at high precision and high throughput

El-Araby

Caliga

2019

Quantum Engineering

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Summary The general approach for emulating quantum algorithms on classical platforms has been through representing them as gate‐based quantum circuits. However, direct implementation of quantum circuits significantly increases the hardware resource utilization and system latency of classical emulators. In this paper, we investigate multiple implementation models alternative to conventional emulation approaches, as feasible solutions to the scalability problem in classical emulation of quantum circuits. In the first model, the quantum circuit functionality is reduced to equivalent, arithmetic (multiply‐and‐accumulate) operations and combined with two computation methods, based on lookup and dynamic generation. In the second model, a kernel operation is extracted from the quantum circuit based on its functionality, and the kernel is iterated through all input quantum states. The proposed emulation models provide space and time optimizations, significantly reducing resource utilizations and latencies and improving scalability. We use these models to develop a highly scalable hardware emulator that is based on reconfigurable technology for efficient simulations of full quantum algorithms and circuits. Our hardware implementations support single precision floating point arithmetic for improved accuracy, and contain fully pipelined designs for high throughput. We investigate quantum algorithms such as quantum Fourier transform and quantum wavelet transform and explore different hardware architectures and optimizations. Experimental results and analysis are provided for the architectures in terms of resource consumption and emulation time. The experiments are carried out on a high‐performance reconfigurable computing system and the obtained results show that the proposed emulator is feasible for running and testing a variety of quantum algorithms.

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FPGA-Based Circuit Model Emulation of Quantum Algorithms

Cited by 36 publications

References 10 publications

Model of a hybrid processor executing C++ with additional quantum functions

Model of a hybrid processor executing C++ with additional quantum functions

A Fast Quantum Computer Simulator Based on Register Reordering

Scaling reconfigurable emulation of quantum algorithms at high precision and high throughput

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