FPGA emulation of quantum circuits

Khalid, Ayesha; Žilić, Željko; Radecka, Katarzyna

doi:10.1109/iccd.2004.1347938

Cited by 52 publications

(33 citation statements)

References 23 publications

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“…Different approaches have been taken to simulate quantum gates and circuits ranging from Programming Languages [11], Hardware Description Language [7], Field Programmable Gate Array [8], and Decision Diagrams [9] among others simulation techniques. This paper presents the mapping of unitary matrices onto a linear systolic array [2].…”

Section: Introductionmentioning

confidence: 99%

Describing Quantum Circuits with Systolic Arrays

Bhave

Montagne

Granados³

2006

IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06)

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Section: Introductionmentioning

confidence: 99%

Describing Quantum Circuits with Systolic Arrays

Bhave

Montagne

Granados³

2006

IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06)

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“…The size of logic circuits of the proposed architecture does not depend on the size of the quantum circuit to be simulated. * * * * * Thus, the proposed architecture is scalable in contrast to the hardware quantum circuit simulators in [1], [8], [11]. Also, the proposed architecture does not use complex inter-connection networks, but uses register reordering in order to select necessary register values.…”

Section: Introductionmentioning

confidence: 99%

“…Indeed, in their experiments, the number of quantum bits of the target quantum circuits is 3. In [1], it is shown that by adding several quantum circuit primitives to those in [8], a lot of quantum algorithms can be simulated quickly and the size of the emulator circuit can be decreased. However, the number of quantum bits and quantum gates that can be simulated are still limited.…”

Section: Introductionmentioning

confidence: 99%

“…Quantum algorithms are often represented by quantum circuits. In [8], an FPGA-based quantum circuit emulator is proposed. For each quantum gate, the corresponding classical sub-circuit that emulates it is implemented on the emulator.…”

Section: Introductionmentioning

confidence: 99%

“…Simulation of quantum computers is a time consuming task, and many simulation methods have been investigated intensively [1]- [16]. Some of them implement the simulator on an LSI [1], [5], [8], [11]. Hardware implementation is considered to be suitable for tasks that run in parallel.…”

Section: Introductionmentioning

confidence: 99%

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A Fast Quantum Computer Simulator Based on Register Reordering

Nakanishi

Matsuyama

Yokoo

2016

IEICE Trans. Inf. & Syst.

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SUMMARY Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on hardware that can process a lot of operations in parallel. In this paper, we propose a hardware quantum computer simulator. The proposed simulator is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implement the simulator on an FPGA. Experiments show that the proposed simulator has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.

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Scaling reconfigurable emulation of quantum algorithms at high precision and high throughput

El-Araby

Caliga

2019

Quantum Engineering

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Summary The general approach for emulating quantum algorithms on classical platforms has been through representing them as gate‐based quantum circuits. However, direct implementation of quantum circuits significantly increases the hardware resource utilization and system latency of classical emulators. In this paper, we investigate multiple implementation models alternative to conventional emulation approaches, as feasible solutions to the scalability problem in classical emulation of quantum circuits. In the first model, the quantum circuit functionality is reduced to equivalent, arithmetic (multiply‐and‐accumulate) operations and combined with two computation methods, based on lookup and dynamic generation. In the second model, a kernel operation is extracted from the quantum circuit based on its functionality, and the kernel is iterated through all input quantum states. The proposed emulation models provide space and time optimizations, significantly reducing resource utilizations and latencies and improving scalability. We use these models to develop a highly scalable hardware emulator that is based on reconfigurable technology for efficient simulations of full quantum algorithms and circuits. Our hardware implementations support single precision floating point arithmetic for improved accuracy, and contain fully pipelined designs for high throughput. We investigate quantum algorithms such as quantum Fourier transform and quantum wavelet transform and explore different hardware architectures and optimizations. Experimental results and analysis are provided for the architectures in terms of resource consumption and emulation time. The experiments are carried out on a high‐performance reconfigurable computing system and the obtained results show that the proposed emulator is feasible for running and testing a variety of quantum algorithms.

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FPGA emulation of quantum circuits

Cited by 52 publications

References 23 publications

Describing Quantum Circuits with Systolic Arrays

Describing Quantum Circuits with Systolic Arrays

A Fast Quantum Computer Simulator Based on Register Reordering

Scaling reconfigurable emulation of quantum algorithms at high precision and high throughput

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