FPGA implementation of back projection algorithm for radar imaging

Crasto, Nieves; Kumar, T. K. Satish; Anuradha, D.; Barua, Paramita; Nemani, Sirisha

doi:10.1109/radar.2013.6651967

Cited by 2 publications

(2 citation statements)

References 4 publications

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“…SAR data processing is computationally intensive, and hardware accelerators, such as graphics processing units (GPUs) and field programmable gate arrays (FPGAs), are required for real-time processing [16][17][18][19][20][21][22][23][24][25][26]. Although GPUs have high processing capabilities, their large power consumption makes them unsuitable for small platforms.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, an FPGA-based SAR system is appropriate for a small platform with limited power. Several SAR imaging algorithms have been implemented, including the range-Doppler algorithm (RDA) [17][18][19], back-projection algorithm (BPA) [20][21][22], and polar format algorithm (PFA) [23][24][25][26]. Although these algorithms are effective, RDA is the most popular one because it is simple, offers easy motion compensation, and provides a flexible tradeoff between accuracy and the number of computations [29].…”

Section: Introductionmentioning

confidence: 99%

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FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

et al. 2021

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In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

et al. 2021

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SARDIMM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging

Kim,

Heo,

Lee

et al. 2024

Applied Sciences

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The range-Doppler algorithm (RDA), a key technique for generating synthetic aperture radar (SAR) images, offers high-resolution images but requires significant memory resources and involves complex signal processing. Moreover, the multitude of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operations in RDA necessitates high bandwidth and lacks data reuse, leading to bottlenecks. This paper introduces a synthetic aperture radar dual in-line memory module (SARDIMM), which executes RDA operations near memory via near-memory processing (NMP), thereby effectively reducing memory accesses, execution time, and energy consumption. The embedded NMP module in SARDIMM optionally supports a combination of FFT, IFFT, and matched filter operations of the RDA for range and azimuth compression. The operator within the NMP module accelerates the FFT by performing two radix-2 single butterfly operations in parallel. The NMP module was implemented and validated on a Xilinx UltraScale+ field-programmable gate array (FPGA) using Verilog-HDL. The acceleration performance of RDA for images of various sizes was evaluated through a simulator modified with gem5 and DRAMSim3 and achieved a 6.34–6.93× speedup and 41.9–48.2% energy savings.

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FPGA implementation of back projection algorithm for radar imaging

Cited by 2 publications

References 4 publications

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

SARDIMM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging

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