FPGA implementation of fast adders using Quaternary Signed Digit number system

Rani, Reena; Singh, L.K.; Sharma, Neelam

doi:10.1109/electro.2009.5441154

Cited by 9 publications

(2 citation statements)

References 7 publications

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“…The use of DEMUX based adders (13) instead of conventional adder for implementation of Vedic multiplier resulted in improvement of power consumption as well as delay. The UT Vedic multiplier with Quaternary Signed Digit (QSD) (14) is implemented, this is best suited for DSP operation such as Fast Fourier Transform, Convolution and Filtering, etc. Palak Yesh et.…”

Section: Introductionmentioning

confidence: 99%

Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier

Sayyad,

Agarkar

2023

IJST

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Objectives: Speed of multiplication in Digital Signal Processing (DSP) applications plays an important role in generating the result quickly. There is scope for reducing the propagation delay in multiplication by designing the multiplier circuit based on the Vedic mathematics (formulas) sutras. This study aims to design the multiplier circuit based on Nikhilam Navatshcaramam Dashath (NND) of Vedic mathematics for improvement in speed, power, and area. Methods: The multiplier circuit based on NND method is designed for the multiplier and multiplicand less than as well as greater than the nearest base in the binary number system. The architecture is designed for both. The proposed multiplier is implemented with VHDL on Vertex-7, Device: XC7VX485T Package: FFG1157, FPGA board using Xilinx ISE 14.7, and its power dissipation is calculated using XPower analyzer. The performance of the proposed multiplier is compared with the conventional array multiplier, Vedic multiplier and also compared with the architecture reported in the literature. Findings: In the proposed architecture n bit multiplier and multiplicand are divided into n/2 bits, two parts, and processed through n/2 bit multiplier and n bit adder. This method converted the n bit multiplication into n/2 bit multiplication and n bit addition. The proposed architecture is efficient in terms of area, delay and power as compared to the array and Vedic Urdhva Tiryakbyham (UT) multiplier. The 4 bit NND multiplier is 26.72 % delay and 47.05 % area efficient as compared to the reported architecture (1) . To compare with other reported architecture, the results are also taken on Artix-7, Device: XC7A100T Package: CSG324, and Spartan-6, Device: XC6SLX4 Package: TQG144 FPGA. The results demonstrate an improvement in processing speed as well as power consumption. This method is a special case of multiplication and is efficient if the multiplicand and multiplier are close to the base value. In this implementation, the multiplier and multiplicand are split into two parts and processed; hence, the algorithm will give the correct result for a specific range of multipliers and multiplicands. The accuracy analysis of the proposed multiplier is also performed for multipliers and multiplicands far away from the base value. The maximum error is 7.94%. Novelty: The architecture used in this system converts n-bit multiplication into n bit addition and https://www.indjst.org/

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Section: Introductionmentioning

confidence: 99%

Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier

Sayyad,

Agarkar

2023

IJST

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“…From the above property, the SD number representation and its arithmetic are suitable for high-precision scienti¯c computation, real-time signal processing, etc. [13][14][15][16][17][18] Moreover, several researches on arithmetic circuit using the SD number representation on FPGA [19][20][21][22][23][24][25][26] are reported. The main disadvantage of the SD number arithmetic is that many logic elements are required when these algorithms are realized on a logic circuit.…”

Section: Introductionmentioning

confidence: 99%

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Tanaka

Suzuki

Wei

2019

J CIRCUIT SYST COMP

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Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

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