FPGA implementation of fast QR decomposition based on givens rotation

Aslan, Semih; Niu, Sufeng; Saniie, Jafar

doi:10.1109/mwscas.2012.6292059

Cited by 29 publications

(28 citation statements)

References 4 publications

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“…Several works, such as in [10] and [7], have proposed a 2D systolic array similar to the one showed in Fig. 2.…”

Section: Implementationsmentioning

confidence: 99%

“…In the literature, there are several papers in which QR factorization has been implemented on FPGA by using this method. Although, serial approaches or linear systolic arrays may be used [6], to achieve high throughput, the most common hardware implementation is through twodimension (2D) systolic arrays, such as in [7], [8], [2], [9], [10], [11]. A 2D systolic array is a parallel grid structure where processing elements (PEs) works in parallel and are locally interconnected.…”

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confidence: 99%

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High-Throughput FPGA Implementation of QR Decomposition

Muñoz

Hormigo

2015

IEEE Trans. Circuits Syst. II

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Abstract-This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are based on the COordinate Rotation DIgital Computer (CORDIC) algorithm. CORDIC computes vector rotations through shifts and additions. This approach allows a continuous computation of QR factorizations with simple hardware. A fixed-point FPGA architecture for 4 × 4 matrices has been optimized by balancing the number of CORDIC iterations with the final error. As a result, compared to other previous proposals for FPGA, our design achieves at least 50% more throughput, and much less resource utilization.

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“…Several works, such as in [10] and [7], have proposed a 2D systolic array similar to the one showed in Fig. 2.…”

Section: Implementationsmentioning

confidence: 99%

mentioning

confidence: 99%

High-Throughput FPGA Implementation of QR Decomposition

Muñoz

Hormigo

2015

IEEE Trans. Circuits Syst. II

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“…To overcome these, many methods are discussed in the literature which approximates these functions using LUT based log domain arithmetic [2,3,7], LUT based Newton-Raphson [4,5], CORDIC based architectures [9], and so forth. In [8], the square root operation is approximated using CORDIC and inverse square root is done by division. Implementation of the division operation and the CORDIC requires higher latency and consumes more area.…”

Section: Background and Related Workmentioning

confidence: 99%

“…In this implementation, the range of the inputs to the LUT-N method is restricted to [0,3] to avoid errors at larger values of input. The proposed method is compared with two different implementations from the literature (CORDIC method [8], NR + CORDIC method [4,5]) for finding square root (sqrt) and inverse square root (isqrt) as mentioned in the Table 2. The error analysis for these blocks is carried out by passing 20, 000 random values generated from MATLAB as inputs to these blocks.…”

Section: Processing Elementsmentioning

confidence: 99%

“…There are different algorithms and architectures proposed in the literature which includes Gram-Schmidt orthogonalization, modified Gram-Schmidt orthogonalization [2,3], Givens rotation [4][5][6][7][8][9][10][11], householder transformations [12], and various other hybrid methods [13,14]. Gram-Schmidt (GS) algorithm offers reduced accuracy and stability in fixed precision environment.…”

Section: Introductionmentioning

confidence: 99%

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Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

Prabhu

Johnson

Rani

2014

International Journal of Reconfigurable Computing

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A Givens rotation based scalable QRD core which utilizes an efficient pipelined and unfolded 2D multiply and accumulate (MAC) based systolic array architecture with dynamic partial reconfiguration (DPR) capability is proposed. The square root and inverse square root operations in the Givens rotation algorithm are handled using a modified look-up table (LUT) based Newton-Raphson method, thereby reducing the area by 71% and latency by 50% while operating at a frequency 49% higher than the existing boundary cell architectures. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for any real matrices of size × , where 4 ≤ ≤ 8 and ≥ by dynamically inserting or removing the partial modules. The evaluation results demonstrate a significant reduction in latency, area, and power as compared to other existing architectures. The functionality of the proposed core is evaluated for a variable length adaptive equalizer.

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