FPGA implementation of high-speed neural network for power amplifier behavioral modeling

Bahoura, Mohammed

doi:10.1007/s10470-014-0263-7

Cited by 8 publications

(7 citation statements)

References 24 publications

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“…The proposed pipelining increased substantiality the operating frequency, but at the cost of the output latency of 36 samples. More details on how delays are inserted and redistributed can be found in our previous works [21,22]. Table 1 shows the hardware resources utilization, the maximum operating frequency, and the power consumption for the Artix-7 XC7A100T FPGA chip, as reported by Xilinx ISE 14.7 tool (Xilinx Inc, San Diego, CA, USA).…”

Section: Pipeliningmentioning

confidence: 99%

Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement

Bahoura

2017

Electronics

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Abstract:In this paper, a new pipelined architecture of the multi-band spectral subtraction algorithm has been proposed for real-time speech enhancement. The proposed hardware has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG), high-level programming tool, and Nexys-4 development board. The multi-band algorithm has been developed to reduce the additive colored noise that does not uniformly affect the entire frequency band of useful signal. All the algorithm steps have been successfully implemented on hardware. Pipelining has been employed on this hardware architecture to increase the data throughput. Speech enhancement performances obtained by the hardware architecture are compared to those obtained by MATLAB simulation using simulated and actual noises. The resource utilization, the maximum operating frequency, and power consumption are reported for a low-cost Artix-7 FPGA device.

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Section: Pipeliningmentioning

confidence: 99%

Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement

Bahoura

2017

Electronics

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“…The neuron activation functions such as sigmoid [2], logarithmic sigmoid [3] or hyperbolic tangent [4] are mostly used in the artificial neural networks. Such functions have easily obtainable derivative, which is important for training process, because that decreases the computational load.…”

Section: Introductionmentioning

confidence: 99%

“…However, the precise implementation of the nonlinearity in FPGA gives cause for concern. The reasonable solutions while solving this issue can be combinational [5], [6], piecewise linear (PWL) [7], [8] or quadratic (PWQ) approximations [2], [9], look-up tables (LUT) synthesized in a logic [10], [11] or stored in on-chip memory [4]. The straightforward implementation of nonlinear function in hardware is not a correct approach, because both exponentiation and division operations are logic and arithmetic resource hungry [5], [11].…”

Section: Introductionmentioning

confidence: 99%

“…The LUT-based approach works much faster than polynomial approximation, since LUT consumes memory. Small LUT is usually implemented in distributed memory, which does not require delay units, but has a limited size [4]. Newest FPGA chips have at least 0.5 MB of on-chip block RAM (BRAM) with one clock cycle latency to access stored data [13].…”

Section: Introductionmentioning

confidence: 99%

“…The accuracy of approximated hyperbolic tangent under various precision input signal and LUT size was investigated in [11]. Depending on the application and required accuracy for the activation function, different sizes LUTs (from 28 samples [10] to 215 samples [4]) are used. This paper presents FPGA implementation of range addressable LUT approximation of hyperbolic tangent function.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

FPGA Implementation of Range Addressable Activation Function for Lattice-Ladder Neuron

Sledevič¹,

Navakauskas²

2016

ElAEE

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FPGA implementation of hyperbolic tangent activation function for multilayer perceptron structure seems attractive; however, there is a lack of preliminary results on the choice of memory size particularly, when LUT of the function is stored in dedicated on-chip block RAM. The aim of this investigation was to get insights on the distortions of the selected neuron model output by the evaluation of transfer function RMS error and neuron output signal mean and maximum errors while changing the gain and memory size of the activation function. Thus, the range addressable activation function for the second order normalized lattice-ladder neuron was implemented in Artix-7 FPGA. Various gain and memory constrains were investigated. The increase of LUT memory size and gain yielded smaller error of output signal and nonlinear influence on the transfer function. 2 kB of BRAM is sufficient to achieve tolerable less than 0.4 % maximum error utilizing only 0.36 % of total on-chip block memory.

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RF Power Amplifier Behavioral Modeling Based on Takenaka–Malmquist–Volterra Series

Schumacher

Lima

Oliveira

2015

Circuits Syst Signal Process

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FPGA implementation of high-speed neural network for power amplifier behavioral modeling

Cited by 8 publications

References 24 publications

Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement

Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement

FPGA Implementation of Range Addressable Activation Function for Lattice-Ladder Neuron

RF Power Amplifier Behavioral Modeling Based on Takenaka–Malmquist–Volterra Series

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