FPGA Implementation of kNN Classifier Based on Wavelet Transform and Partial Distance Search

Yeh, Yao-Jung; Li, Hui-Ya; Hwang, Wen-Jyi; Fang, Chiung‐Yao

doi:10.1007/978-3-540-73040-8_52

Cited by 24 publications

(11 citation statements)

References 6 publications

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“…In [24], a digital hardware CL architecture based on hardware PDS in the wavelet domain [31] is proposed. Although the architecture is able to perform online neuron updating in hardware, it can only process one training vector at a time.…”

Section: Related Workmentioning

confidence: 99%

Efficient pipelined architecture for competitive learning

Hung

Hwang

et al. 2011

Journal of Parallel and Distributed Computing

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Section: Related Workmentioning

confidence: 99%

Efficient pipelined architecture for competitive learning

Hung

Hwang

et al. 2011

Journal of Parallel and Distributed Computing

Self Cite

View full text Add to dashboard Cite

“…Furthermore it covers only the trivial special case M = 1 (single-dimensional vectors) and is difficult to generalize to any dimensionality. An FPGA implementation based on the wavelet transform has been presented in Yeh et al [2007]. It achieves fast computation while reducing the area complexity by combining subspace Partial Distance Search (PDS) with bit-plane reduction and multiple-coefficient accumulation techniques.…”

Section: Introductionmentioning

confidence: 99%

Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

Stamoulias

Μανωλάκος

2013

ACM Trans. Embed. Comput. Syst.

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We designed a variety of k-nearest-neighbor parallel architectures for FPGAs in the form of parameterizable soft IP cores. We show that they can be used to solve large classification problems with thousands of training vectors, or thousands of vector dimensions using a single FPGA, and achieve very high throughput. They can be used to flexibly synthesize architectures that also cover: 1NN classification (vector quantization), multishot queries (with different k), LOOCV cross-validation, and compare favorably to GPU implementations. To the best of our knowledge this is the first attempt to design flexible IP cores for the popular kNN classifier. ACM Reference Format:Stamoulias, I. and Manolakos, E. S. 2013. Parallel architectures for the kNN classifier -Design of soft IP cores and FPGA implementations.

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“…K nearest neighbor (KNN) classifier is one of the simplest machine learning algorithms for classifying samples based on the NN rule. Hardware implementations of KNN that exploit parallel processing and pipelining have been reported in [22]- [24]. However, KNN needs to find the k smallest distances to the test sample among all references which are the whole training data.…”

Section: Introductionmentioning

confidence: 99%

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

Koide

Mattausch

2012

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, we propose a hardware solution for overcoming the problem of high computational demands in a nearest neighbor (NN) based multi-prototype learning system. The multiple prototypes are obtained by a high-speed K-means clustering algorithm utilizing a concept of software-hardware cooperation that takes advantage of the flexibility of the software and the efficiency of the hardware. The one nearest neighbor (1-NN) classifier is used to recognize an object by searching for the nearest Euclidean distance among the prototypes. The major deficiency in conventional implementations for both K-means and 1-NN is the high computational demand of the nearest neighbor searching. This deficiency is resolved by an FPGA-implemented coprocessor that is a VLSI circuit for searching the nearest Euclidean distance. The coprocessor requires 12.9% logic elements and 58% block memory bits of an Altera Stratix III E110 FPGA device. The hardware communicates with the software by a PCI Express (×4) local-bus-compatible interface. We benchmark our learning system against the popular case of handwritten digit recognition in which abundant previous works for comparison are available. In the case of the MNIST database, we could attain the most efficient accuracy rate of 97.91% with 930 prototypes, the learning speed of 1.3 × 10 −4 s/sample and the classification speed of 3.94 × 10 −8 s/character.

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FPGA Implementation of kNN Classifier Based on Wavelet Transform and Partial Distance Search

Cited by 24 publications

References 6 publications

Efficient pipelined architecture for competitive learning

Efficient pipelined architecture for competitive learning

Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

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