Frequency Limitations of First-Order $g_{m} - RC$ All-Pass Delay Circuits

Abstract

All-pass filter circuits can implement a time delay but, in practice, show delay and gain variations versus frequency, limiting their useful frequency range. This brief derives analytical equations to estimate this frequency range, given a certain maximum allowable budget for variation in delay and gain. We analyze and compare two well-known g m − RC first-order allpass circuits, which can be compactly realized in CMOS technology and relate their delay variation to the main pole frequency. Modeling parasitic poles and putting a constraint on gain variation, equations for the maximum achievable pole frequency and delay variation versus frequency are derived. These equations are compared with simulation and used to design and compare delay cells satisfying given design goals.

Compact Cascadable g m -C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency

“…a 1 st order all-pass filter: The 1 st order all-pass transfer function can be realized both with g m -RC filters [2], [11] (see Fig.3) and the g m -C filter presented in this paper and in [12]. In [13] a benchmarking method has been proposed to compare delay cells based on f =0 . This method is re-used here to show that the g m -C delay cell of [12] has better performance than other published designs.…”

“…Then the transfer function can be rewritten as: (8) Using the analysis in [13], the maximum usable pole frequency f p is defined as the frequency where the gain roll-off with respect to DC is less than ∆H p , resulting in:…”

“…To estimate f p and compare it with the delay cells reported in [2] and [11] (benchmarked in [13]), the same technology (UMC 180nm CMOS), same H p =1dB and same f t,M1 =12.4GHz for the NMOS transistors have been used. The choice H p =1dB is only for comparison to [13], and it will be reduced in section IV where several delay cells will be cascaded.…”

“…The choice H p =1dB is only for comparison to [13], and it will be reduced in section IV where several delay cells will be cascaded. Substituting the values in (10), the result is f p 2 GHz, which is a 4x improvement compared to other circuits in [13]. shift occurs w.r.t.…”

“…Table 2 shows a comparison between the simulated results of this work and the simulated results of other reported g m -RC delay cells (refer to Fig.3). The technology used in every case is UMC 180nm to compare to [13]. The V GS of NMOS transistors for all circuits are the same to maintain equal f t,n =12.4GHz for fair comparison.…”