Frequent value compression in data caches

Yang, Jun; Zhang, Youtao; Gupta, Rajiv

doi:10.1145/360128.360154

Cited by 141 publications

(114 citation statements)

References 8 publications

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“…As of yet, no mechanism has been proposed to implement a dynamic dictionary for caches; instead the dictionaries proposed so far are loaded statically via profiling or are "trained" for a small period of time but remain static once they are loaded with values [1,14,23,25,26]. Dynamic (adaptive) dictonaries are reported in the context of bus compression [2,7,17,19,20,24].…”

Section: Dynamic Dictionary and Compressed Data Consistencymentioning

confidence: 99%

“…Yang and Gupta [25] proposed a compressed L1 cache design where each set can store either one uncompressed line or two compressed lines. A static dictionary was used in their design.…”

Section: Design Issues Of High-performance Dfvc (Hp-dfvc)mentioning

confidence: 99%

“…L2/L3 compression is therefore a useful technique for the foreseeable future and especially for future CMP architectures. Alternatively, compression can be used to free space in the cache which can then be translated to power savings [13,22,23,25].…”

Section: Introductionmentioning

confidence: 99%

“…One such simple, yet effective, mechanism is the dictionary (or directory) for frequent values [20,23,25,26]. A frequent-value dictionary stores the program's frequent values (e.g., the 32-bit value "0") and replaces all their occurrences in the cache with the respective dictionary indices (e.g., 8-bit indices for a 256-entry dictionary).…”

Section: Introductionmentioning

confidence: 99%

“…However, until now, no mechanism has been proposed to implement a dynamic dictionary for caches [23,24]; in other words, a dictionary whose contents can adapt to the requirements of the running program. The dictionaries proposed so far for caches are loaded statically via profiling or are "trained" for a small period of time to detect and store frequent values for the remainder of a program's run [23,25,26]. In practice, such a static approach is avoided by designers since it is cumbersome in real systems.…”

Section: Introductionmentioning

confidence: 99%

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Dynamic Dictionary-Based Data Compression for Level-1 Caches

Κεραμίδας

Aisopos

2006

Architecture of Computing Systems - ARCS 2006

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Abstract. Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. While several techniques have been proposed for L2 compression, L1 compression is an elusive goal. This is due to L1's sensitivity to latency and the inability to create compression schemes that are both fast and adaptable to program behavior, i.e. dynamic. In this paper, we propose the first dynamic dictionary-based compression mechanism for L1 data caches. Our design solves the problem of keeping the compressed contents of the cache and the dictionary entries consistent, using a timekeeping decay technique. A dynamic compression dictionary adapts to program behavior without the need of profiling techniques and/or training phases. We compare our approach to previously proposed static dictionary techniques and we show that we surpass them in terms of power, hit ratio and energy delay product.

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Section: Dynamic Dictionary and Compressed Data Consistencymentioning

confidence: 99%

“…Yang and Gupta [25] proposed a compressed L1 cache design where each set can store either one uncompressed line or two compressed lines. A static dictionary was used in their design.…”

Section: Design Issues Of High-performance Dfvc (Hp-dfvc)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dynamic Dictionary-Based Data Compression for Level-1 Caches

Κεραμίδας

Aisopos

2006

Architecture of Computing Systems - ARCS 2006

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Enabling Partial‐Cache Line Prefetching through Data Compression

Zhang¹,

Gupta²

2005

High‐Performance Computing

Self Cite

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Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buffers and causes significant memory traffic increase. In this paper we propose a new prefetching scheme which improves performance without increasing memory traffic or requiring prefetch buffers. We observe that a significant percentage of dynamically appearing values exhibit characteristics that enable their compression using a very simple compression scheme. The bandwidth freed by transferring values from lower levels in memory hierarchy to upper levels in compressed form is used to prefetch additional compressible values. These prefetched values are held in vacant space created in the data cache by storing values in compressed form. Thus, in comparison to other prefetching schemes, our scheme does not introduce prefetch buffers or increase the memory traffic. In comparison to a baseline cache that does not support prefetching, on average, our cache design reduces the memory traffic by 10%, reduces the data cache miss rate by 14%, and speeds up program execution by 7%.

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Reducing Cache Hardware by Focusing on Data Redundancy

Kobayashi

Matsukawa

Shimomura

et al. 2014

Elect Comm in Japan

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SUMMARY There is one reason to utilize cache that mitigates processor performance limitation comes from data transfer bandwidth. Recently, cache size expansion is required in this use because data transfer bandwidth requirement is increasing for recent large data size and multi‐core trends. However, cache size expansion is unwelcome because it causes problems arising from circuit area and power consumption viewpoint. This paper focuses a data redundancy with the goal of reducing cache size and proposes a mechanism that does not store redundant data into cache. The proposed mechanism divides data into higher bit and lower bit that stored into higher cache and lower cache, respectively. We reduced higher cache size to half size by keeping 46% redundant data in higher bit area not to store into higher cache. The evaluation results show that the proposed mechanism increases IPC by 3.3% on average compared with same circuit area conventional cache under SPECCPU2000 benchmarks.

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Frequent value compression in data caches

Cited by 141 publications

References 8 publications

Dynamic Dictionary-Based Data Compression for Level-1 Caches

Dynamic Dictionary-Based Data Compression for Level-1 Caches

Enabling Partial‐Cache Line Prefetching through Data Compression

Reducing Cache Hardware by Focusing on Data Redundancy

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