Fully coupled 3-D device simulation of negative capacitance FinFETs for sub 10 nm integration

Ota, Hiroyuki; Ikegami, Tsutomu; Hattori, Junichi; Fukuda, Koichi; Migita, Shinji; Toriumi, Akira

doi:10.1109/iedm.2016.7838403

Cited by 81 publications

(29 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An internal metal gate (IMG) has been proposed to be inserted between the NC layer and the underlying MOSFET. It has been found that the IMG induced fringing capacitance (that helps induce further polarization in the NC layer) can help improve SS 21 . The physical mechanism of this effect is well captured by the developed analysis in this work (Supplementary Note 8).…”

Section: Resultsmentioning

confidence: 99%

“…Previous attempts at understanding the workings of NC-FETs either assumed the total FET gate capacitance to be a constant 7,18 , i.e., the bias-dependent channel capacitance was ignored, or were focused on performing intensive numerical simulations [21][22][23][24][25] or complex analytical modeling 26,27 of a specific NC-FET such as NC-FinFET and NC-2DFET etc., in which the generic device physics, design rule and major challenges of NC-FETs get obscured. In this work, we analytically formulate the slope of the transfer characteristics of a generic NC-FET structure, from which a physics-rich but concise picture is innovatively extracted for "visualizing" the intriguing device physics and design space of NC-FETs.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Is negative capacitance FET a steep-slope logic switch?

2020

View full text Add to dashboard Cite

The negative-capacitance field-effect transistor(NC-FET) has attracted tremendous research efforts. However, the lack of a clear physical picture and design rule for this device has led to numerous invalid fabrications. In this work, we address this issue based on an unexpectedly concise and insightful analytical formulation of the minimum hysteresis-free subthreshold swing (SS), together with several important conclusions. Firstly, well-designed MOSFETs that have low trap density, low doping in the channel, and excellent electrostatic integrity, receive very limited benefit from NC in terms of achieving subthermionic SS. Secondly, quantumcapacitance is the limiting factor for NC-FETs to achieve hysteresis-free subthermionic SS, and FETs that can operate in the quantum-capacitance limit are desired platforms for NC-FET construction. Finally, a practical role of NC in FETs is to save the subthreshold and overdrive voltage losses. Our analysis and findings are intended to steer the NC-FET research in the right direction.

show abstract

Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Is negative capacitance FET a steep-slope logic switch?

2020

View full text Add to dashboard Cite

show abstract

“…The simulation and modeling study of negative capacitance in the MOSFETs has been investigated in the literature [19]- [23]. Also, some studies have been done to investigate the short channel effect in inversion-mode NC FETs, a majority of them being based on detailed simulations [24]- [26]. However, none of them is an analytical charge-based model and there is no evidence of modeling and investigating the short channel effect in NC JLFETs based on solving 2D Poisson-Boltzmann relationships.…”

Section: Introductionmentioning

confidence: 99%

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

Rassekh

Sallèse

Jazaeri

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, our model predicts that the negative capacitance minimizes short channel effects and enhances current overdrive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels. Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.

show abstract

“…FeFET with sub-60mV/dec SS also exhibits unique device characteristics such as reverse drain-induced barrier lowering (R-DIBL) and negative differential resistance (NDR) [6], [19]- [21]. Previously, these special behaviors were predicted by the QSNC theory and regarded as the indication of the stabilized NC in ferroelectric [22]- [24]. The theory of NC needs to give reasonable explanation not only for steep SS but also R-DIBL and NDR consistently.…”

Section: Introductionmentioning

confidence: 99%

Physical Mechanisms of Reverse DIBL and NDR in FeFETs With Steep Subthreshold Swing

Jin

Saraya

Hiramoto

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

We have investigated transient I d − V g and I d − V d characteristics of ferroelectric field-effect transistor (FeFET) by simulation with ferroelectric model considering polarization switching dynamics. We show transient negative capacitance (TNC) with polarization reversal and depolarization effect can result in sub-60mV/dec subthreshold swing (SS), reverse drain-induced barrier lowering (R-DIBL), and negative differential resistance (NDR) without traversing the quasi-static negative capacitance (QSNC) region of the S-shaped polarization-voltage (P − V) predicted by single-domain Landau theory. Moreover, the mechanisms of R-DIBL and NDR based on the TNC theory are discussed in detail. The results demonstrated in this work can be a possible explanation for the mechanism of previously reported negative capacitance field-effect transistor (NCFET) with sub-60mV/dec SS, R-DIBL, and NDR.

show abstract

Fully coupled 3-D device simulation of negative capacitance FinFETs for sub 10 nm integration

Cited by 81 publications

References 4 publications

Is negative capacitance FET a steep-slope logic switch?

Is negative capacitance FET a steep-slope logic switch?

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

Physical Mechanisms of Reverse DIBL and NDR in FeFETs With Steep Subthreshold Swing

Contact Info

Product

Resources

About