Fully Digital Background Calibration Technique for Channel Mismatches in TIADCs

Ta, Van-Thanh; Thi, Yen Hoang; Duc, Han Le; Hoang, Van‐Phuc

doi:10.1109/nics.2018.8606871

Cited by 3 publications

(6 citation statements)

References 11 publications

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“…However, the TIADC performance in [31] needed to be further improved. In our recent work [32], a calibration technique was proposed for all offset, gain, and timing mismatches with preliminary results without detail analysis, hardware validation, and state-of-the-art comparison. Moreover, in [33], channel deviations were corrected by a similar approach.…”

Section: U Xmentioning

confidence: 99%

“…Next, the gain and timing errors are calibrated by combining a Hadamard transform block and a bandpass derivative filter. Instead of using the ideal differential filter as in [16,32], this work proposes to use a bandpass derivative filter to improve the TIADC performance. This filter allows the proposed TIADC to be applied directly in the next generation direct sampling receivers such as software defined radios, broadband satellite receivers, and sub-sampling receivers.…”

Section: U Xmentioning

confidence: 99%

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An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Hoang

Pham

et al. 2020

Electronics

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The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.

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Section: U Xmentioning

confidence: 99%

Section: U Xmentioning

confidence: 99%

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Hoang

Pham

et al. 2020

Electronics

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“…Researchers have proposed a lot of methods about TIADC mismatch error [3]- [7].The timing mismatch can usually be corrected by a mixed correction method or digital domain interpolation method [3,4,5]. This method completed calibration in the analog domain, but the control clock's hardware circuit needed to be added.…”

Section: Introductionmentioning

confidence: 99%

Calibration of timing mismatch for TIADC based on error table and fractional delay filter

Shi

Xie

2023

J. Phys.: Conf. Ser.

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In this paper, we presents a correcting method based on an error table and fractional delay filter for correcting timing mismatch in a time-interleaved analog-to-digital converter (TIADC). This method uses the ramp signal to estimate timing mismatch and the error table storage error value. A Farrow structure fractional delay filter is utilized to implement the calibration of mismatch. Simulation results show that this method can realize the correction of timing mismatch and suppress the spurious component effectively with a good correction effect.

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“…However, the main limitation of this technique is that there is an overlap between the basic function and desired signal when the input signal is single-tone spaced at kM  . Instead of calibrating gain and timing mismatches by combining Hadamard transform and LMS algorithm in [19] or combining modulation matrix and LMS algorithm in [20], in this paper, we calibrate the gain mismatch by calculating the power ratio of the sub-ADC with the reference ADC. Firstly, the offset mismatch is calibrated by taking the average of sub-ADC output samples.…”

Section: Introductionmentioning

confidence: 99%

“…Firstly, the offset mismatch is calibrated by taking the average of sub-ADC output samples. Finally, the timing error is calibrated by using the Hadamard transform and LMS algorithm as in [19]. In [19], [20], a calibration technique was proposed with preliminary results without detail analysis and state ofthe-art comparison.…”

Section: Introductionmentioning

confidence: 99%

All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

Ta¹,

Hoang²,

Tran³

2019

EAI Endorsed Transactions on Industrial Networks and Intelligen

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This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog to digital converters (TIADCs). The averaging technique is used to remove the offset mismatch at each channel. The gain mismatch is calibrated by calculating the power ratio of the sub-ADC over the reference ADC. Timing skew is compensated by using Hadamard transform for error correction and least mean squares (LMS) algorithm for estimation of the clock skew. The performance improvement of TIADCs employing these techniques is demonstrated through numerical simulations.

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Fully Digital Background Calibration Technique for Channel Mismatches in TIADCs

Cited by 3 publications

References 11 publications

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Calibration of timing mismatch for TIADC based on error table and fractional delay filter

All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

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