Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration

Rivoir, Jochen

doi:10.1109/test.2006.297713

Cited by 25 publications

(16 citation statements)

References 14 publications

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“…Rivoir analyzed the stochastic calibration using a frequency selectable ring oscillator depicted in Fig. 6 and a clock generator [16,17]. We proposed a stochastic calibration architecture using two ring oscillators shown in Fig.…”

Section: Stochastic Calibrationmentioning

confidence: 99%

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Analog/mixed-signal circuit design in nano CMOS era

Kobayashi

Aoki

Katoh

et al. 2014

IEICE Electron. Express

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This paper describes analog/mixed-signal circuit design in the nano CMOS era. Digitally-assisted analog technology is becoming more important, and as an example, our fully digital FPGA implementation of a TDC with self-calibration is shown. Since pure analog circuits are still present and "good" device modeling is required for their designs, device modeling technology for nano CMOS with complicated behavior is also reviewed.

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Section: Stochastic Calibrationmentioning

confidence: 99%

“…6. Ring-oscillator with 1024 selectable oscillation periods generating calibration events for a VDLbased TDC [16].…”

Section: Implementation To Fpgamentioning

confidence: 99%

Analog/mixed-signal circuit design in nano CMOS era

Kobayashi

Aoki

Katoh

et al. 2014

IEICE Electron. Express

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“…In calibration mode, the relative variation (ratio) among delay elements are measured with the histogram method. [4,5,6] In measurement mode, the TDC digital output is corrected based on the histogram data to improve the TDC linearity.…”

Section: Flash-type Tdc With Ring Oscillatormentioning

confidence: 99%

“…It uses a delay line composed of CMOS inverter buffer delays; however their absolute and relative values vary due to process, supply voltage and temperature (PVT) variations, and this degrades the TDC linearity. Hence self-calibration techniques are required [5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Experimental verification of timing measurement circuit with self-calibration

Chujo

Hirabayashi

et al. 2014

19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings

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This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC using a Programmable Systemon-Chip (PSoC), and measurement results show that TDC linearity is improved by the self-calibration. All TDC circuits, as well as the self-calibration circuits can be implemented as digital circuits, even by using FPGA instead of full custom ICs, so this is ideal for fine CMOS implementation with short design time.

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“…Short time interval measurement is widely used in space science [1][2][3], high-energy physics [4][5][6], laser range finding [7] and test equipment [8][9][10]. The accurate time interval measurement technology, especially technology with a picosecond resolution is particularly important [11].…”

mentioning

confidence: 99%

High-resolution short time interval measurement system implemented in a single FPGA chip

2011

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This study proposes a high-resolution short time interval measurement system based on the Vernier delay line (VDL) method. It should be noted that the programmable delay elements (PDEs) in the Xilinx field programmable gate arrays (FPGAs) provide a novel realization of delay lines. The delay lines can provide an accurate delay difference of 50 ps, which is process, voltage and temperature (PVT) invariant. An excellent consistency for the delay lines can be achieved by adjusting the timing and layout to minimize the measurement errors. The resolution achieved was 58 ps. Experimental results indicate a measurement standard deviation of 36 ps, a differential nonlinearity (DNL) of 36 ps and integral nonlinearity (INL) of 14 ps. The system features high accuracy, easy implementation and low cost.short time interval measurement system, field programmable gate array, programmable delay elements, Vernier delay line Citation:Wang H, Zhang M, Liu J. High-resolution short time interval measurement system implemented in a single FPGA chip.

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Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration

Cited by 25 publications

References 14 publications

Analog/mixed-signal circuit design in nano CMOS era

Analog/mixed-signal circuit design in nano CMOS era

Experimental verification of timing measurement circuit with self-calibration

High-resolution short time interval measurement system implemented in a single FPGA chip

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