Fully integrated embedded DRAM technologies with high performance logic and commodity DRAM cells for system-on-a-chip

Koike, H.; Takato, H.; Hiyama, K.; Yoshida, Shinji; Harakawa, H.; Kokubun, K.; Shimabukuro, T.; Kato, S.; Tamaoki, M.; Okano, Hitoshi; Sato, Hisakazu; Morimasa, Y.; Yamamoto, Tetsuya; Tanaka, Mitsugu; Kumagai, J.; Yakabe, O.; Naruse, H.; Kamijo, Hiroshi; Tomioka, K.; Ishiuchi, H.

doi:10.1109/vtsa.1999.786045

Cited by 3 publications

(1 citation statement)

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“…As in the case of commodity DRAM, WSi/Poly gate electrode and non-silicided source/drain are used. In the 0.25um generation, the same device performance as that for 0.25um logic is finally achieved due to the addition of Ti salicide process for the entire device, with the exception of the memory cell region because the retention characteristics of memory cell are sensitive to the junction leakage caused by silicided junction[1] [2]. Chip performance has been progressively improved throughout the development of 0.5um, 0.35um and 0.25um eDRAM.…”

Section: Development Trends Of Edrammentioning

confidence: 99%

Embedded DRAM Technologies

Takato

2000

30th European Solid-State Device Research Conference

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Issues and development trends respecting embedded DRAM(eDRAM) are reviewed by referring to real implementations for 0.5um, 0.35um and 0.25um generations.Chip performance has been progressively improved throughout the development of 0.5um, 0.35um and 0.25um eDRAM. However, the number of process steps has increased compared to that for commodity DRAM. To avoid increasing cost and achieve the highest possible device performance, future directions of the embedded DRAM technologies, including MOSFET structure, memory cells, product cost and performance, are also discussed.

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Section: Development Trends Of Edrammentioning

confidence: 99%