Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm

Yi, Jee‐Jeon; Park, Karam; Park, Joonseok; Ro, Won Woo

doi:10.1007/978-3-642-00641-8_19

Cited by 5 publications

(11 citation statements)

References 5 publications

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“…It is obvious that the architectures in [20, 21] are better, in some areas than the proposed one, but their design philosophy is very different than ours (they are architectures for high‐speed applications). In [22], an architecture of Present cipher is presented for encryption‐only operation and its hardware implementation.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 96%

“…So, reliable comparisons in term of the covered area between the proposed architecture and the other previously published architectures are impossible. Table 4 gives comparisons with previously published architectures for SEED cipher [7,8], [20,21] and for Present cipher [22][23][24]. Present is part of the ISO/IEC 29192-2:2012 standard [25] that specifies lightweight block ciphers suitable for IoT.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

“…This implementation consumes 8268 LUTs. Finally, in [21] a fully pipelined implementation is proposed with a datapath that also handles a 128-bit input Message and Key. It uses 16 cascade rounds with pipeline registers between the rounds.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

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8‐bit serialised architecture of SEED block cipher for constrained devices

Pirpilidis

Pyrgas

Kitsos

2020

IET Circuits, Devices & Systems

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This study presents an 8-bit serialised architecture of SEED block cipher for constrained devices. The circuit utilises 356 FPGA slices and 447 1-bit registers flip-flops (FFs) in the BASYS3 board, operates with an 8-bit datapath and is aimed for use on area constraints devices. In order to keep the usage of hardware resources to a minimum but, at the same time, achieve a high level of security, the key generation process of SEED is implemented through an on-the-fly procedure. In addition, the necessary S-boxes are implemented using composite field arithmetic without using any block RAMs, resulting in a very compact implementation. The proposed architecture achieves a maximum frequency equal to 125 MHz with a total latency of 280 clock cycles and a throughput up to 57.1 Mbps for encryption or decryption.

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Section: Fpga Implementation and Resultsmentioning

confidence: 96%

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

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8‐bit serialised architecture of SEED block cipher for constrained devices

Pirpilidis

Pyrgas

Kitsos

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…The design occupies 80% chip area of ALTERA I0KE. On the other hand, a more recent paper by Yi et al (2009) presented a result of 6.4 Gbps throughput on a Virtex-V XC5LX110T while occupying 53% of the chip area. The number of slice LUTs used is 36,678 (53%) and the number of slice flip-flops used is 5314 (7%).…”

Section: Seed (Seed 128)mentioning

confidence: 93%

“…There are no hardware implementation examples using the . Given that the new SEED ciphers are similar with just different key-lengths, the hardware examples can be referred to: Yi et al (2009) andYoung-Ho et al (2000).…”

Section: Seed 192/256mentioning

confidence: 99%