Fundamental performance limits and scaling of a CMOS passive double-balanced mixer

Komoni, K.; Sonkusale, Sameer; Dawe, G.

doi:10.1109/newcas.2008.4606380

Cited by 18 publications

(5 citation statements)

References 8 publications

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“…Conventional voltage passive mixers, as described in [3], are usually driven by a sinusoidal LO waveform or a 50% duty cycle square wave. These mixers often provide a low conversion gain 2/π maximum value) which degrades the receiver NF performances.…”

Section: Sampling Mixer Principlementioning

confidence: 99%

“…According to (1), increases when D gets lower and tends toward 1 as the duty cycle D tends to 0. As a result, using a sampling mixer rather than a conventional CMOS voltage passive mixer allows to break the 2/π conversion gain limitation [3] to ideally reach the value of 1. This property of the sampling mixer increases the gain of the front-end before the baseband amplification.…”

Section: Sampling Mixer Principlementioning

confidence: 99%

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A New 77 GHz Sampling Mixer in 28-nm FD-SOI CMOS Technology for Automotive Radar application

Flete

Viallon

Cathelin

et al. 2022

2022 IEEE/MTT-S International Microwave Symposium - IMS 2022

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This paper presents a low-IF sampling mixer topology based on a new pulse shaper and designed for automotive radar application. The sampling mixer operation principle is described. Then an original pulse shaper topology convenient for a 77 GHz sampling operation is proposed and implemented in 28-nm FD-SOI CMOS technology. Measurement results show a 1dB input-referred compression power (ICP1dB) of +6.7 dBm and a 9.1 dB Noise Figure (NF) with a conversion gain of -0.7 dB. The power consumption of the mixer is 10 mW on a 1V supply.

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Section: Sampling Mixer Principlementioning

confidence: 99%

Section: Sampling Mixer Principlementioning

confidence: 99%

A New 77 GHz Sampling Mixer in 28-nm FD-SOI CMOS Technology for Automotive Radar application

Flete

Viallon

Cathelin

et al. 2022

2022 IEEE/MTT-S International Microwave Symposium - IMS 2022

View full text Add to dashboard Cite

show abstract

“…For this reason, all inputs must preserve a high amplitude level. In order to reach the ideal value of À9.943 dB (Komoni, Sonkusale, and Dawe 2008) for the voltage conversion gain, the device performing the multiplication should not introduce any undesired output frequencies owing to its nonlinear characteristics or its high frequency limitations. Furthermore, there is a trade-off between noise figure (NF) and required LO drive.…”

Section: Frequency Doublersmentioning

confidence: 99%

A 90 nm CMOS 15/60 GHz frequency quadrupler

Souliotis¹,

Plessas²,

Liakou³

et al. 2013

International Journal of Electronics

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The design and characterisation of a 60 GHz frequency quadrupler implemented in a conventional 90 nm CMOS technology is presented. The proposed fully differential frequency quadrupler is formed by properly combining a 15 GHz to 30 GHz doubler, two 30 GHz amplifiers, a polyphase filter, a 30 to 60 GHz doubler and two 60 GHz amplifiers. The proposed design is based on a differential architecture and achieves enhanced characteristics in terms of harmonics rejection, bandwidth, power consumption and die area. Conversion loss of 9.3 dBm at 60 GHz with 1.1 dBm input power is achieved. The 3 dB bandwidth lies between 51.5 GHz and 61 GHz, while the total current consumption is 100 mA from a 1.2 V supply voltage for the fully balanced implementation.

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“…The voltage conversion gain of a doublebalanced passive mixer is expressed as [9] , 2 2 20log( ( where Z L is the load impedance, R on is the impedance when the switch is on and Z off is the impedance when the switch is off. R on /|Z L | is assumed <<1 in (3).…”

Section: B Passive Mixermentioning

confidence: 99%

A 70 GHz 10.2 mW self-demodulator for OOK modulation in 65-nm CMOS technology

Baltus

Zeijl

et al. 2010

IEEE Custom Integrated Circuits Conference 2010

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A 70.86 to 79.29 GHz low-power selfdemodulator for on-off-keying (OOK) modulation is realized in TSMC 65-nm CMOS technology. By using a frequencysweeping injection-locked oscillator (IJLO), the OOK modulated 70 GHz signal is demodulated by itself in a passive mixer and an 8.43 GHz bandwidth is achieved at 10.2 mW power consumption from a 1-V supply. The conversion gain is 10 dB and constant over the entire bandwidth. The core area of the chip is 0.072 mm 2 .Index Terms -Self-demodulator, injection-locked oscillator, frequency-sweeping tuning, on-off-keying, low power, passive mixer, CMOS.

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Fundamental performance limits and scaling of a CMOS passive double-balanced mixer

Cited by 18 publications

References 8 publications

A New 77 GHz Sampling Mixer in 28-nm FD-SOI CMOS Technology for Automotive Radar application

A New 77 GHz Sampling Mixer in 28-nm FD-SOI CMOS Technology for Automotive Radar application

A 90 nm CMOS 15/60 GHz frequency quadrupler

A 70 GHz 10.2 mW self-demodulator for OOK modulation in 65-nm CMOS technology

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