GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

Nary, K.R.; Long, S.I.

doi:10.1109/4.156439

Cited by 24 publications

(5 citation statements)

References 6 publications

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“…Communication is local and strictly forward, and pipe-lining can be extended to gate-level. This makes high speed operation possible, and enables clocked gate technologies like for instance GaAs TDFL [12] to be utilized. It is highly modular and regular, enabling efficient implementation of module generators.…”

Section: Resultsmentioning

confidence: 99%

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A systolic ON-LINE non-restoring division scheme

Andersen

Nielsen²,

Olsen³

1994

Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94

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Section: Resultsmentioning

confidence: 99%

“…Computation in the ON-LINE MSDF addition is strictly forward, enabling additional pipe-lining down to gate level. This property allows very high speed operation, and it is essential, if the algorithm is to be implemented in a pure clocked gate technology, like for instance GaAs TDFL [12].…”

Section: On-line Arithmeticmentioning

confidence: 99%

A systolic ON-LINE non-restoring division scheme

Andersen

Nielsen²,

Olsen³

1994

Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94

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“…That is because 3 of the 4 states in the NOR gate have a static power loss, while there are only 1 of the 4 states in the NAND gate, as seen from Table 2. Therefore, both NAND gate and NOR gate may be simultaneously needed for building the complex logic circuit [23,24]. Fig.…”

Section: Proposed Manchester-encoded Data Transmission Circuitmentioning

confidence: 99%

Manchester‐encoded data transmission circuit integrated by metal–oxide TFTs suitable for 13.56 MHz radio‐frequency identification tag application

Chen

Wang

et al. 2018

IET Circuits, Devices & Systems

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This study proposes a Manchester-encoded data transmission circuit suitable for 13.56 MHz radio-frequency identification (ID) tags integrated by indium-zinc-oxide thin-film transistors (TFTs). All the modules in the circuit are only constructed by two types of logic units: NOT gate and NOR gate. The 16 bit ID data are stored in the read-only-memory circuits realised by a fixed TFTs array. The 16 bit ID data are encoded by Manchester module as the output of the Manchester-encoded data transmission circuit with a bit rate of 103 kbps. The chip area is 6.5 mm 2 with the total number of gates as 76 and the sum of the transistors as 300. Moreover, the power consumption is 3.8 mW at VDD = 5 V.

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“…For example the dynamic design in [2] needs both negative and positive power supplies. The TDFL design in [6] works on two clock phases with added design complexity due to sensitivity to clock skew and area penalty for routing of two clock signals. The TTDL design in [5] uses a trickle transistor to compensate for the leakage from the precharged node.…”

Section: Introductionmentioning

confidence: 99%

High speed GaAs subsytem design using feed through logic

Montiel–Nelson

Armas

Sarmiento

et al. 1999

Proceedings of the Conference on Design, Automation and Test in Europe

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In this paper design of fast arithmetic circuits using GaAs based Feed Through Logic (FTL) family [1] is presented. A modified version of FTL termed Differential FTL (DFTL) is introduced and basic aspects of design methologies using FTL are discussed. A 4-bit ripple-carry adder is designed and its performance is evaluated against other similar reported works in terms of, device count, chip area, delay, clock rate, and power consumption. It is shown how arithmetic circuits based on FTL outperform the evaluated performance. A 4-bit magnitude comparator is designed and performance evaluated against four cascaded 1-bit comparators.

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GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

Cited by 24 publications

References 6 publications

A systolic ON-LINE non-restoring division scheme

A systolic ON-LINE non-restoring division scheme

Manchester‐encoded data transmission circuit integrated by metal–oxide TFTs suitable for 13.56 MHz radio‐frequency identification tag application

High speed GaAs subsytem design using feed through logic

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