Gallium-Nitride Semiconductor Technology and Its Practical Design Challenges in Power Electronics Applications: An Overview

Vecchia, Mauricio Dalla; Ravyts, Simon; Broeck, Giel Van den; Driesen, Johan

doi:10.3390/en12142663

Cited by 63 publications

(45 citation statements)

References 74 publications

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“…A central challenge of power electronics today is to address the continuously rising demands for safe and reliable control, conversion and distribution of energy, while maximizing the efficiency. Switched-mode power conversion strategies, with myriad applications [ 1 , 2 , 3 , 4 , 5 ], are now universally preferred over the simpler linear conversion methods due to the advantages of better flexibility, safety, and importantly, higher efficiency. The core requirement for efficient power conversion thus translates directly to highly efficient power transistors that can sustain repeated OFF/ON switching transitions with minimal switching and resistive losses.…”

Section: Introductionmentioning

confidence: 99%

Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

et al. 2021

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The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

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Section: Introductionmentioning

confidence: 99%

Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

et al. 2021

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“…11a it becomes clear that the efficiency difference between the X-FOM-predicted efficiency and the real efficiency can be reduced by simply adding a Kelvin connection [42]. As semiconductor technology has improved (and especially with the faster switching speed provided by WBG devices [49,50]), better device packages with reduced parasitics that increase switching performance and reduce overvoltages [44,45,51] have become available (e.g., devices with planar bond wires [52] or direct PCB connection [53,54] for SiC devices and surface-mounted devices for GaN HEMTs [55]). With the integration of the gate driver circuitry, as shown in Fig.…”

Section: Future Challenges Of Wbg Devicesmentioning

confidence: 99%

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Anderson

Zulauf

Kolar

et al. 2020

IEEE Open J. Power Electron.

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Figures-of-merit (FOMs) are widely-used to compare power semiconductor materials and devices and to motivate research and development of new technology nodes. These material-and device-specific FOMs, however, fail to directly translate into quantifiable performance in a specific power electronics application. Here, we combine device performance with specific bridge-leg topologies to propose the extended FOM, or X-FOM, a figure-of-merit that quantifies bridge-leg performance in multi-level (ML) topologies and supports the quantitative comparison and optimization of topologies and power devices. To arrive at the proposed X-FOM, we revisit the fundamental scaling laws of the on-state resistance and output capacitance of power semiconductors to first propose a revised device-level semiconductor Figure-of-Merit (D-FOM). The D-FOM is then generalized to a multi-level topology with an arbitrary number of levels, output power, and input voltage, resulting in the X-FOM that quantitatively compares hard-switched semiconductor stage losses and filter stage requirements across different bridgeleg structures and numbers of levels, identifies the maximum achievable efficiency of the semiconductor stage, and determines the loss-optimal combination of semiconductor die area and switching frequency. To validate the new X-FOM and showcase its utility, we perform a case study on candidate bridge-leg structures for a three-phase 10 kW photovoltaic (PV) inverter, with the X-FOM showing that (a) the minimum hard-switching losses are an accurate approximation to predict the theoretically maximum achievable efficiency and relative performance between bridge-legs and (b) the 3-level bridge-leg outperforms the 2-level configuration, despite utilizing a SiC MOSFET with a lower D-FOM than in the 2-level case.

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“…Otro campo por considerar es el desarrollo de las nuevas generaciones de semiconductores basados en tecnologías como el Carburo de Silicio (SiC) [6] y Nitruro de Galio (GaN) [7] que prometen mejorar en un factor de ⁓10 las características térmicas y eléctricas de los actuales componentes semiconductores de potencia. Al igual que el Silicio (Si) es sus inicios, estas tecnologías no están maduras y como tal se requiere mucho refinamiento de los procesos de fabricación, los mismos que son retroalimentados a partir de las pruebas de fiabilidad [8], [9].…”

Section: Ta Perspectivasunclassified

Aplicación de Mediciones de Ruido de Baja Frecuencia para el Análisis de Efectos de Estrés Térmico y Eléctrico en Dispositivos de Potencia

Berrones¹,

Macías²,

Buenaño³

et al. 2020

Perspectivas

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Este documento presenta el estudio del efecto del estrés térmico y eléctrico en dispositivos semiconductores de potencia a través de mediciones de ruido de baja frecuencia. Se aplico una prueba de Polarización Inversa a Alta Temperatura (HTRB por sus siglas en inglés) a los dispositivos de potencia, determinando sus características eléctricas. Las herramientas utilizadas para este estudio fueron una fuente de tensión variable hasta 1200V diseñada para la aplicación de estrés eléctrico, un módulo de temperatura compuesto por un mini calentador y un módulo de control diseñado para la aplicación de estrés térmico junto con el analizador de parámetros Keithley 4200-SCSn para la caracterización corriente-voltaje y un sistema de medición de ruido de baja frecuencia para caracterización de canales conductivos en dispositivos electrónicos. Los resultados indican un mayor nivel de ruido flicker después de la aplicación del estrés sobre los MOSFETs estudiados, que se relacionan con cambios en el voltaje de umbral producto del estrés aplicado, correlacionando directamente dichos parámetros.

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Gallium-Nitride Semiconductor Technology and Its Practical Design Challenges in Power Electronics Applications: An Overview

Cited by 63 publications

References 74 publications

Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Aplicación de Mediciones de Ruido de Baja Frecuencia para el Análisis de Efectos de Estrés Térmico y Eléctrico en Dispositivos de Potencia

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