GaN-based double-gate (DG) sub-10-nm MOSFETs: effects of gate work function

Mehedi, Ibrahim M.; Alshareef, Abdulaziz; Hasan, Md. Tanvir

doi:10.1007/s10825-017-1119-z

Cited by 11 publications

(6 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The parameters which are essential to calculate the Figure of Merits (FOMs) of GaAs and GaSb based DG-JLMOSFETs have been extracted. The detailed extracted formulas and procedures are mentioned in our previous work [49]. The GaAs and GaSb based UTB DG-JLMOSFET structures that have been studied in this work is different from the FinFET or gate-all-around FET as the UTB structure significantly considers the QCE.…”

Section: Computational Methodologymentioning

confidence: 99%

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

Islam

Hasan²,

Islam

et al. 2021

IEEE Access

Self Cite

View full text Add to dashboard Cite

In this paper, the performance of GaAs and GaSb based sub-10 nm double-gate junctionless metal-oxide-semiconductor field-effect transistors (DG-JLMOSFETs) have been studied for highperformance switching applications. The quantum transmitting boundary method (QTBM) has been considered for electron transport, and the band structures are accounted for sp3d5s * tight-binding modeling. The channel thickness, t ch is varied from 1.7 to 4.7 nm to evaluate the device figure of merits (FOMs). The thinner channel's device shows a lower OFF-state current, while the ticker channel device allows a higher ON-state current. The threshold voltage is approximately 0.4 V for GaAs DG-JLMOSFETs with t ch = 1.7 nm, whereas it reduces to ∼0.05 V for that of t ch = 4.7 nm. Similar characteristics have been shown in GaSb devices. Besides, a significant impact of t ch on the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) is found in GaSb DG-JLMOSFETs compared with those of GaAs devices. The devices show a higher leakage-power dissipation in both channel materials and low-intrinsic delay for thicker t ch due to a substantial amount of energy drop. The above results indicate that III-V-based DG-JLMOSFETs are very promising for next-generation high-performance switching technology.INDEX TERMS GaAs, GaSb, double gate, junctionless MOSFETs, nano-scaled device, short-channel effects (SCEs), high-performance switching.

show abstract

Section: Computational Methodologymentioning

confidence: 99%

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

Islam

Hasan²,

Islam

et al. 2021

IEEE Access

Self Cite

View full text Add to dashboard Cite

show abstract

“…For example, at V GS = 0.2 V, N D =1×1019 cm − 3 shows a drain current of 10 − 13 A/µm and N D = 1×10 17 cm −3 shows a drain current of 10 − 16 A/µm.To demonstrate the effects of various N D on the ON-state and OFF-state of the device more speci cally, the ON-current, I ON , and ON-OFF current ratio, I ON /I OFF values are plotted in Fig.4(a). It is seen that, N D = 1×10 19 cm − 3 results in the highest I ON (0.9 mA/µm) and the lowest I ON /I OFF (7.56×1012 ). Whereas N D = 1×10 17 cm − 3 results in the lowest I ON (0.02 mA/µm) and the highest I ON /I= (7.18×1014 ).…”

mentioning

confidence: 93%

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

Hasan,

Islam,

Hasan

2024

Heliyon

View full text Add to dashboard Cite

“…For example, at V GS = 0.2 V, N D =1×10 19 cm − 3 shows a drain current of 10 − 13 A/µm and N D = 1×10 17 cm −3 shows a drain current of 10 − 16 A/µm.To demonstrate the effects of various N D on the ON-state and OFF-state of the device more speci cally, the ON-current, I ON , and ON-OFF current ratio, I ON /I OFF values are plotted in Fig.4(a). It is seen that, N D = 1×1019 cm − 3 results in the highest I ON (0.9 mA/µm) and the lowest I ON /I OFF (7.56×1012 ). Whereas N D = 1×10 17 cm − 3 results in the lowest I ON (0.02 mA/µm) and the highest I ON /I= (7.18×1014 ).…”

mentioning

confidence: 93%

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

Hasan,

Islam,

Hasan

2023

Preprint

Self Cite

View full text Add to dashboard Cite

This study aims to explore the potential of the GaN-based junction-less double-gate (JLDG) MOSFETs in resolving the limitations by tuning its doping profile, ND, and gate work function, Ф to realize low-power switching applications. Device figure-of-merits (FOMs) such as ION, ION/IOFF, subthreshold slope (SS), and drain-induced barrier lowering (DIBL) have been evaluated. The highest ION is 0.9 mA/µm, which resulted in ND = 1×1019 cm-3. The device behaviour is also impacted significantly by changing gate work function, Ф. The OFF-state current, IOFF of 1.24×10-16 A/µm and power dissipation of 9.69×10-17 W/µm have been found for Ф = 5.11 eV (Au). In addition, the highest ION/IOFF of 7.56×1012 indicates the GaN-based JLDG MOSFETs promising for next-generation low-power logic switching applications.

show abstract

GaN-based double-gate (DG) sub-10-nm MOSFETs: effects of gate work function

Cited by 11 publications

References 21 publications

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

Contact Info

Product

Resources

About