Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

Veloso, A.; Hellings, Geert; Cho, M. J.; Simoen, Eddy; Devriendt, K.; Paraschiv, Vasile; Vecchio, E.; Tao, Zheng; Versluijs, Janko; Souriau, Laurent; Dekkers, Harold; Brus, S.; Geypen, J.; Lagrain, Pieter; Bender, Hugo; Eneman, G.; Matagne, Philippe; Keersgieter, A. De; Wen, Fang; Collaert, N.; Thean, A.

doi:10.1109/vlsit.2015.7223652

Cited by 48 publications

(21 citation statements)

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“…As a reference, the value for a trigate nFinFET, fabricated with a similar process flow is also given. The following conclusions can be drawn: except for the IM NW devices, lower noise PSD can be found for the GAA transistors compared with FinFETs (FF) [4], [8], [22], [23]. The observed reduction in noise PSD is not orders of magnitude as in other reports and has been related to the preferential conduction inside the uniformly doped nanowire [6].…”

Section: Low-frequency Noise Performancementioning

confidence: 66%

“…The single horizontal NWFETs have been processed on 300 mm diameter SOI substrates as described in detail elsewhere [4], [22], [23]. The fin width was 22-23 nm and the height 30 nm.…”

Section: Measurementsmentioning

confidence: 99%

“…Initial studies mainly focused on single horizontal nanowires, fabricated on a silicon-on-insulator (SOI) substrate [1]- [5]. More recently, the noise behavior of so-called Junctionless (JL) transistors has been discussed [4], [6]- [8]. Double NW nMOSFETs on bulk silicon substrates were shown to suffer from access resistance 1/f noise at high drain current [9], a typical problem for nanowire transistors [10].…”

Section: Introductionmentioning

confidence: 99%

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Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

Simoen

Oliveira

Agopian

et al. 2020

2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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This work reviews the low-frequency noise performance of different flavors of silicon Gate-All-Around Nanowire (NW) (or Nanosheet-NS) transistors. For the horizontal devices, the 1/f-like noise is dominated by the number fluctuations mechanism, so that the Power Spectral Density (PSD) is directly proportional with the trap density in the gate stack. The impact of different process options and device architectures (junctionless versus inversion mode) is discussed. Overall, it is found that the average 1/f noise PSD is reducing going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices and, finally, vertical NW FETs. In the latter case, white noise may dominate the lowfrequency noise spectrum.

show abstract

Section: Low-frequency Noise Performancementioning

confidence: 66%

“…The single horizontal NWFETs have been processed on 300 mm diameter SOI substrates as described in detail elsewhere [4], [22], [23]. The fin width was 22-23 nm and the height 30 nm.…”

Section: Measurementsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

Simoen

Oliveira

Agopian

et al. 2020

2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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show abstract

“…Si has been scaled below 10 nm in multigate 4,5 and silicon-oninsulator (SOI) device technologies, 6,7 but its thickness cannot be reduced indefinitely and larger surface-to-bulk ratios will impact the behavior of Si. In general, surface physics cannot be discounted as thickness approaches 5 nm.…”

Section: Introductionmentioning

confidence: 99%

Exploring conductivity in ex-situ doped Si thin films as thickness approaches 5 nm

MacHale

Meaney

Kennedy

et al. 2019

Journal of Applied Physics

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“…Germanium (Ge) is a promising candidate of sub-14 nm technology for the p channel device due to its high hole mobility. 3D device structures such as Fin-FETs, nanowires [7][8][9][10][11][12] are used to strengthen the electrostatic control and improve the subthreshold properties. However, serious self-heating effects (SHE) are predictable [13][14][15][16][17][18] due to new materials and non-planar structures.…”

Section: Introductionmentioning

confidence: 99%

Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

Yin

Shen

Jiang

et al. 2017

Sci. China Inf. Sci.

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In this paper, self-heating effects (SHE) in nanoscale Ge p-channel FinFETs with Si substrate are evaluated by TCAD simulation. Hydrodynamic transport with modified mobilities and Fourierś law of heat conduction with modified thermal conductivities are used in the simulation. Ge p-channel single-fin FinFET devices with different S/D extension lengths and fin heights, and multi-fin FinFETs with different fin numbers and fin pitches are successively investigated. Boundary thermal resistances at source, drain and gate contacts are set to 2000 µm 2 K/W and the substrate thermal boundary condition is set to 300 K so that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) 14 nm Ge p-channel single-fin FinFETs with a 47 nm fin pitch experience 9.7% on-state current degradation. (ii) Considering the same input power, FinFETs with a longer S/D extension length show a higher lattice temperature and a larger on-state current degradation. (iii) Considering the same input power, FinFETs with a taller fin height show a higher lattice temperature. (iv) The temperature in multi-fin FinFET devices will first increase then saturate with the increasing fin number. At last, thermal resistances in Ge p-channel single-fin FinFETs and multi-fin FinFETs are investigated.

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Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

Cited by 48 publications

References 1 publication

Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

Exploring conductivity in ex-situ doped Si thin films as thickness approaches 5 nm

Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

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