Gate Bias Stress-Induced Threshold Voltage Shift Effect of a-IGZO TFTs with Cu Gate

Liu, Xiang; Wang, Lisa Ling; Ning, Ce; Hu, Hehe; Yang, Wei; Wang, Ke; Yoo, Seong-Yeon; Zhang, Shengdong

doi:10.1109/ted.2014.2362850

Cited by 22 publications

(2 citation statements)

References 13 publications

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“…The typical performance of the IGZO TFTs with a similar structure prepared by conventional DC or RF magnetron sputtering are summarized in Table 4 for comparison. When fabricated by DC or RF MS at room temperature, the TFTs exhibited an inferior performance [ 19 , 20 ] Generally, a post-annealing treatment at 250–450 °C is required to improve the performance [ 19 , 20 , 21 , 22 , 23 , 24 ]. In contrast, the IGZO TFTs prepared by HiPIMS have a small SS value, even if they were fabricated at room temperature without post-annealing or other treatment, implying that the defects in the IGZO channel were reduced.…”

Section: Resultsmentioning

confidence: 99%

The Enhanced Performance of Oxide Thin-Film Transistors Fabricated by a Two-Step Deposition Pressure Process

Zhao,

Yan,

Wang

et al. 2024

Nanomaterials

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It is usually difficult to realize high mobility together with a low threshold voltage and good stability for amorphous oxide thin-film transistors (TFTs). In addition, a low fabrication temperature is preferred in terms of enhancing compatibility with the back end of line of the device. In this study, α-IGZO TFTs were prepared by high-power impulse magnetron sputtering (HiPIMS) at room temperature. The channel was prepared under a two-step deposition pressure process to modulate its electrical properties. X-ray photoelectron spectra revealed that the front-channel has a lower Ga content and a higher oxygen vacancy concentration than the back-channel. This process has the advantage of balancing high mobility and a low threshold voltage of the TFT when compared with a conventional homogeneous channel. It also has a simpler fabrication process than that of a dual active layer comprising heterogeneous materials. The HiPIMS process has the advantage of being a low temperature process for oxide TFTs.

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Section: Resultsmentioning

confidence: 99%

The Enhanced Performance of Oxide Thin-Film Transistors Fabricated by a Two-Step Deposition Pressure Process

Zhao,

Yan,

Wang

et al. 2024

Nanomaterials

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“…Secondly, the operation of GOA circuits needs more stable and uniform TFTs compared to that of pixel switches, especially for large size TV applications [11]. Small threshold voltage variation of a-IGZO TFTs induced by processes or long-term operation might result in deterioration of the circuits [12], [13]. To address these issues, many circuit designs have been proposed in the past, which, however, increase the circuit complexity and thus the layout area [14]- [17].…”

Section: Introductionmentioning

confidence: 99%

Robust Gate Driver on Array Based on Amorphous IGZO Thin-Film Transistor for Large Size High-Resolution Liquid Crystal Displays

Wang²,

Zhou³

et al. 2019

IEEE J. Electron Devices Soc.

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Amorphous IGZO thin-film transistors (TFTs) in an etch stop layer (ESL) structure was processed on 2500 mm × 2200 mm size substrate. The fabricated devices exhibit enhancement mode characteristics, and excellent uniformity over large area. The presented good operational stabilities under both positive gate bias temperature stress (PBTS) and negative gate bias temperature stress (NBTS) tests can well meet the requirements for pixel switching. However, considering even threshold voltage shift under long term positive bias stress might affect proper operation of the gate driver on array (GOA), a design with a pulse gating scheme is proposed, consisting of 13 TFTs and 1 capacitor, to avoid long term continuous bias stressing of the TFT. With the proposed GOA design, a 32-inch QUHD (7680×4320) highresolution liquid crystal display (LCD) panel with a 7 mm wide bezel is achieved. The reliability of the GOA circuit is well proved through standard aging tests.

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A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

Jung

Lee

et al. 2019

J Soc Info Display

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In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (VGS) value for pull‐down units. The results showed all the VOUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable VOUT voltage when the threshold voltage for all TFTs was changed from −6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved VOUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.

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Gate Bias Stress-Induced Threshold Voltage Shift Effect of a-IGZO TFTs with Cu Gate

Cited by 22 publications

References 13 publications

The Enhanced Performance of Oxide Thin-Film Transistors Fabricated by a Two-Step Deposition Pressure Process

The Enhanced Performance of Oxide Thin-Film Transistors Fabricated by a Two-Step Deposition Pressure Process

Robust Gate Driver on Array Based on Amorphous IGZO Thin-Film Transistor for Large Size High-Resolution Liquid Crystal Displays

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

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