Gate capacitance coupling of singled-walled carbon nanotube thin-film transistors

Abstract

The electrostatic coupling between singled-walled carbon nanotube (SWNT) networks/arrays and planar gate electrodes in thin-film transistors (TFTs) is analyzed both in the quantum limit with an analytical model and in the classical limit with finite-element modeling. The computed capacitance depends on both the thickness of the gate dielectric and the average spacing between the tubes, with some dependence on the distribution of these spacings. Experiments on transistors that use sub-monolayer, random networks of SWNTs verify certain aspects of these calculations. The results are important for the development of networks or arrays of nanotubes as active layers in TFTs and other electronic devices.

Microwave purification of large-area horizontally aligned arrays of single-walled carbon nanotubes

“…3h 17,50 ). The magnitudes of the computed power inside each SWNT in the array are directly related to the values of r. For this particular geometry, SWNT-SWNT coupling, although present 44 , does not have a significant effect on the results. The non-contact case (Fig.…”

“…The results allow quantitative extraction of mobilities. The average values that use rigorous calculations of the gate capacitance [42][43][44][45] (Supplementary Note 2) and neglect contact resistances are B1,600 cm 2 V À 1 s À 1 as shown in the inset of Fig. 2e (weighted average B1,100 cm 2 V À 1 s À 1 for various devices, Supplementary Fig.…”

Fully Printed and Encapsulated SWCNT-Based Thin Film Transistors via a Combination of R2R Gravure and Inkjet Printing

“…Field effect mobilities were extracted from measured transfer characteristics in the linear region (V ds = −1 V) using the parallel plate model for the capacitance (C ox =3 8n Fc m −2 ). Use of this model for the capacitance likely underestimates the actual mobility as it overestimates the capacitance; 51 however it does not require an accurate estimate of the SWCNT network density.…”

Capacitance-Voltage Characteristics of Thin-film Transistors Fabricated with Solution-Processed Semiconducting Carbon Nanotube Networks

“…3c. Also presented are the parallel-plate capacitance (black dashed line), which was also experimentally measured using onchip capacitors fabricated with the same dielectric layer as the TFTs (see Additional file 1: Figure S4a), and that calculated from the cylindrical model (blue dashed lines) using the equation reported in the literature [15] with an estimated average nanotube diameter of 1.4 nm. From the results, it is obvious that the parallel-plate model overestimates the gate capacitance while the cylindrical model underestimates it.…”