Gate-controlled reversible rectifying behaviour in tunnel contacted atomically-thin MoS2 transistor

Abstract

Atomically thin two-dimensional semiconducting materials integrated into van der Waals heterostructures have enabled architectures that hold great promise for next generation nanoelectronics. However, challenges still remain to enable their applications as compliant materials for integration in logic devices. Here, we devise a reverted stacking technique to intercalate a wrinkle-free boron nitride tunnel layer between MoS2 channel and source drain electrodes. Vertical tunnelling of electrons therefore makes it possible to suppress the Schottky barriers and Fermi level pinning, leading to homogeneous gate-control of the channel chemical potential across the bandgap edges. The observed features of ambipolar pn to np diode, which can be reversibly gate tuned, paves the way for future logic applications and high performance switches based on atomically thin semiconducting channel.

Tuning Electronic Structure of Single Layer MoS2 through Defect and Interface Engineering

“…14 Meanwhile, as defects and substrates alter the band structure of MoS 2 , targeted selection of substrates can help engineer various electronic devices that can be designed and engineered, such as tunneling field-effect transistors. 63,64 In addition, using oxide substrates such as CeO 2 in this work, electronic and photonic devices tunable by temperature can potentially be fabricated and operated.…”

Charge carrier injection and transport engineering in two-dimensional transition metal dichalcogenides

“…7h ). 39 , 50 , 128 Alternatively, metal oxides provide a fruitful path to unpin the Fermi level. For example, high work function metal Pd/MoO x /MoS 2 contacts or the Co catalytic oxidation of multilayer MoS 2 into MoO x nanoparticles can enable ambipolar transport owing to efficient hole injection into MoS 2 ; consequently asymmetric Ni/MoS 2 /MoO x /Pd diodes show a rectification ratio of 10 5 and an ideality factor of 1.4.…”

Introducing Electrode Contact by Controlled Micro-Alloying in Few-Layered GaTe Field Effect Transistors

“…Over the past several years, tremendous efforts have been carried out to optimise the contact resistance for 2D nanoelectronics [20][21][22][23][24][25][26][27][28][29] such as using work function-matched metals [26], phase engineering [24,30], van der Waals heterostructure [21,31], selective etching [23,32], tunnelling effect [20,25,28], etc. The motivation of polymorph engineering or van der Waals contact is to decrease the contact barrier or increase carrier mobility, yet these methods always need sophisticated manipulation skills, and an easy methodology to tackle this problem is highly desired.…”